x393  1.0
FPGAcodeforElphelNC393camera
buf_xclk_mclk16_393 Module Reference
Inheritance diagram for buf_xclk_mclk16_393:

Static Public Member Functions

Always Constructs

ALWAYS_202  ( xclk )
ALWAYS_203  ( mclk )
ALWAYS_204  ( xclk )

Public Attributes

Inputs

mclk  
xclk  
rst  
din   [ 15 : 0 ]
din_stb  

Outputs

dout   reg [ 15 : 0 ]
dout_stb   reg

Signals

reg[ 1 : 0 ]  wa
reg[ 1 : 0 ]  wa_mclk
reg[ 1 : 0 ]  wa_mclk_d
reg  rst_mclk
reg[ 1 : 0 ]  ra
reg[ 1 : 0 ]  ra_next
reg  inc_ra
wire[ 15 : 0 ]  pre_dout
reg[ 15 : 0 ]  fifo_4x16_ram [ 0 : 3 ]

Detailed Description

Definition at line 41 of file buf_xclk_mclk16_393.v.

Member Function Documentation

ALWAYS_202 (   xclk  
)
Always Construct

Definition at line 59 of file buf_xclk_mclk16_393.v.

ALWAYS_203 (   mclk  
)
Always Construct

Definition at line 64 of file buf_xclk_mclk16_393.v.

ALWAYS_204 (   xclk  
)
Always Construct

Definition at line 80 of file buf_xclk_mclk16_393.v.

Member Data Documentation

mclk
Input

Definition at line 42 of file buf_xclk_mclk16_393.v.

xclk
Input

Definition at line 43 of file buf_xclk_mclk16_393.v.

rst
Input

Definition at line 44 of file buf_xclk_mclk16_393.v.

din [ 15 : 0 ]
Input

Definition at line 45 of file buf_xclk_mclk16_393.v.

din_stb
Input

Definition at line 46 of file buf_xclk_mclk16_393.v.

dout reg [ 15 : 0 ]
Output

Definition at line 47 of file buf_xclk_mclk16_393.v.

dout_stb reg
Output

Definition at line 48 of file buf_xclk_mclk16_393.v.

wa
Signal

Definition at line 50 of file buf_xclk_mclk16_393.v.

wa_mclk
Signal

Definition at line 51 of file buf_xclk_mclk16_393.v.

wa_mclk_d
Signal

Definition at line 52 of file buf_xclk_mclk16_393.v.

rst_mclk
Signal

Definition at line 53 of file buf_xclk_mclk16_393.v.

ra
Signal

Definition at line 54 of file buf_xclk_mclk16_393.v.

ra_next
Signal

Definition at line 55 of file buf_xclk_mclk16_393.v.

inc_ra
Signal

Definition at line 56 of file buf_xclk_mclk16_393.v.

pre_dout
Signal

Definition at line 57 of file buf_xclk_mclk16_393.v.

fifo_4x16_ram [ 0 : 3 ]
Signal

Definition at line 79 of file buf_xclk_mclk16_393.v.


The documentation for this Module was generated from the following files: