52 TODO Comments from cmd_encod_tiled_rd, update 53 Minimal ACTIVATE period =4 Tcm or 10ns, so maximal no-miss rate is Tck=1.25 ns (800 MHz) 54 Minimal window of 4 ACTIVATE pulses - 16 Tck or 40 (40 ns), so one ACTIVATE per 8 Tck is still OK down to 1.25 ns 55 Reads are in 16-byte colums: 1 8-burst (16 bytes) in a row, then next row, bank inc first. Then (if needed) - next column 56 Number of rows should be >=5 (4 now for tCK=2.5ns to meet tRP (precharge to activate) of the same bank (tRP=13ns) 57 Can read less if just one column 58 TODO: Maybe allow less rows with different sequence (no autoprecharge/no activate?) Will not work if row crosses page boundary 62 1: Most tile heights cause timing violation. Valid height mod 8 can be 0,6,7 (1,2,3,4,5 - invalid) 63 2: With option "keep_open" there should be no page boundary crossings, caller only checks the first line, and if window full width 64 is not multiple of CAS page, page crossings can appear on other than first line (fix caller to use largest common divider of page and 65 frame full width? Seems easy to fix 72 parameter CMD_DONE_BIT=
10,
// VDT BUG: CMD_DONE_BIT is used in a function call parameter! 78 // programming interface 84 input [
5:
0]
num_cols_in_m1,
// number of 16-pixel columns to read (rows first, then columns) - 1 87 input start,
// start generating commands 88 output reg [
31:
0]
enc_cmd,
// encoded command SuppressThisWarning VivadoSynthesis: [Synth 8-3332] Sequential element cmd_encod_tiled_wr.enc_cmd_reg[11,9,6,4:3,1] is unused and will be removed from module cmd_encod_tiled_wr. 89 output reg enc_wr,
// write encoded command 101 localparam ENC_CMD_SHIFT=
6;
// [7:6] - command: 0 -= NOP, 1 - WRITE, 2 - PRECHARGE, 3 - ACTIVATE 110 localparam LOOP_FIRST=
6;
// address of the first word in a loop 111 localparam LOOP_LAST=
7;
// address of the last word in a loop 113 localparam CMD_NOP=
0;
// 3-bit normal memory RCW commands (positive logic) 120 reg [
2:
0]
bank;
// memory bank; 128 // reg gen_run_d; // to output "done"? 131 reg [
ROM_WIDTH-
1:
0]
rom_r;
// SuppressThisWarning VivadoSynthesis: [Synth 8-3332] Sequential element cmd_encod_tiled_wr.rom_r_reg[8,0] is unused and will be removed from module cmd_encod_tiled_wr. 138 reg [
FULL_ADDR_NUMBER-
4:
0]
top_rc;
// top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act 141 wire pre_act;
//1 cycle before optional ACTIVATE 143 reg [
5:
0]
scan_row;
// current row in a tile (valid @pre_act) 144 reg [
5:
0]
scan_col;
// current 16-byte column in a tile (valid @pre_act) 162 // always @ (posedge clk) begin 163 // if (!gen_run) cut_buf_rd <= 0; 164 // else if ((gen_addr==(LOOP_LAST-1)) && loop_continue) cut_buf_rd <= 1; //******* 168 {
top_rc,
bank}:
// can not work if ACTIVATE is next after ACTIVATE in the last row (single-row tile) 175 assign rom_cmd=
rom_r[
ENC_CMD_SHIFT+:
2];
// & {enable_act,1'b1}; // disable bit 1 if activate is disabled (not the first column) 188 always @ (
posedge clk)
begin 250 // ROM-based (registered output) encoded sequence 251 always @ (
posedge clk)
begin 272 always @ (
posedge clk)
begin 287 3'b0},
// [14:0] addr; // 15-bit row/column address 291 full_cmd[
2:
0],
// rcw; // RAS/CAS/WE, positive logic 293 1'b0,
// cke; // disable CKE 294 rom_r[
ENC_SEL],
// sel; // first/second half-cycle, other will be nop (cke+odt applicable to both) 295 rom_r[
ENC_DQ_DQS_EN],
// dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 296 rom_r[
ENC_DQ_DQS_EN],
// dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 298 1'b0,
// dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 299 1'b0,
// buf_wr; // connect to external buffer (but only if not paused) 300 rom_r[
ENC_BUF_RD],
// buf_rd; // connect to external buffer (but only if not paused) 301 rom_r[
ENC_NOP],
// nop; // add NOP after the current command, keep other data 303 else enc_cmd <=
func_encode_skip (
// encode pause 304 {{
CMD_PAUSE_BITS-
2{
1'b0}},
rom_skip[
1:
0]},
// skip; // number of extra cycles to skip (and keep all the other outputs) 305 pre_done,
// done, // end of sequence 306 3'b0,
// bank (here OK to be any) 308 1'b0,
// cke; // disable CKE 309 rom_r[
ENC_SEL],
// sel; // first/second half-cycle, other will be nop (cke+odt applicable to both) 310 rom_r[
ENC_DQ_DQS_EN],
// dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 311 rom_r[
ENC_DQ_DQS_EN],
// dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 313 1'b0,
// dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 314 1'b0,
// buf_wr; // connect to external buffer (but only if not paused) 315 rom_r[
ENC_BUF_RD],
// buf_rd; // connect to external buffer (but only if not paused) 367 function [
31:
0]
func_encode_cmd;
368 input [
14:
0]
addr;
// 15-bit row/column address 369 input [
2:
0]
bank;
// bank (here OK to be any) 370 input [
2:
0]
rcw;
// RAS/CAS/WE, positive logic 371 input odt_en;
// enable ODT 372 input cke;
// disable CKE 373 input sel;
// first/second half-cycle, other will be nop (cke+odt applicable to both) 374 input dq_en;
// enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 375 input dqs_en;
// enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 376 input dqs_toggle;
// enable toggle DQS according to the pattern 377 input dci;
// DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 378 input buf_wr;
// connect to external buffer (but only if not paused) 379 input buf_rd;
// connect to external buffer (but only if not paused) 380 input nop;
// add NOP after the current command, keep other data 381 input buf_rst;
// connect to external buffer (but only if not paused) 384 addr[
14:
0],
// 15-bit row/column address 386 rcw[
2:
0],
// RAS/CAS/WE 387 odt_en,
// enable ODT 388 cke,
// may be optimized (removed from here)? 389 sel,
// first/second half-cycle, other will be nop (cke+odt applicable to both) 390 dq_en,
// enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 391 dqs_en,
// enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 392 dqs_toggle,
// enable toggle DQS according to the pattern 393 dci,
// DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 394 buf_wr,
// phy_buf_wr, // connect to external buffer (but only if not paused) 395 buf_rd,
// phy_buf_rd, // connect to external buffer (but only if not paused) 396 nop,
// add NOP after the current command, keep other data 397 buf_rst // Reserved for future use 402 function [
31:
0]
func_encode_skip;
403 input [
CMD_PAUSE_BITS-
1:
0]
skip;
// number of extra cycles to skip (and keep all the other outputs) 404 input done;
// end of sequence 405 input [
2:
0]
bank;
// bank (here OK to be any) 406 input odt_en;
// enable ODT 407 input cke;
// disable CKE 408 input sel;
// first/second half-cycle, other will be nop (cke+odt applicable to both) 409 input dq_en;
// enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 410 input dqs_en;
// enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 411 input dqs_toggle;
// enable toggle DQS according to the pattern 412 input dci;
// DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 413 input buf_wr;
// connect to external buffer (but only if not paused) 414 input buf_rd;
// connect to external buffer (but only if not paused) 415 input buf_rst;
// connect to external buffer (but only if not paused) 417 func_encode_skip=
func_encode_cmd (
419 bank[
2:
0],
// bank (here OK to be any) 420 3'b0,
// RAS/CAS/WE, positive logic 421 odt_en,
// enable ODT 423 sel,
// first/second half-cycle, other will be nop (cke+odt applicable to both) 424 dq_en,
// enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 425 dqs_en,
// enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 426 dqs_toggle,
// enable toggle DQS according to the pattern 427 dci,
// DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 428 buf_wr,
// connect to external buffer (but only if not paused) 429 buf_rd,
// connect to external buffer (but only if not paused) 4533row_col_bankreg[FULL_ADDR_NUMBER-1:0]
4510colreg[COLADDR_NUMBER-4:0]
[ADDRESS_NUMBER-1:0] 4477start_row
4488FULL_ADDR_NUMBERADDRESS_NUMBER+COLADDR_NUMBER
4518gen_addrreg[ROM_DEPTH-1:0]
4513num_cols128_m1reg[5:0]
4538next_rowcol_wwire[ADDRESS_NUMBER+COLADDR_NUMBER-4:0]
4519rom_rreg[ROM_WIDTH-1:0]
4524top_rcreg[FULL_ADDR_NUMBER-4:0]
4509rowreg[ADDRESS_NUMBER-1:0]
4534col_bankwire[COLADDR_NUMBER-1:0]
4514rowcol_increg[FRAME_WIDTH_BITS:0]
[FRAME_WIDTH_BITS:0] 4479rowcol_inc_in
4540row_col_bank_next_wwire[FULL_ADDR_NUMBER-1:0]
[COLADDR_NUMBER-4:0] 4478start_col