52 Minimal ACTIVATE period =4 Tcm or 10ns, so maximal no-miss rate is Tck=1.25 ns (800 MHz) 53 Minimal window of 4 ACTIVATE pulses - 16 Tck or 40 (40 ns), so one ACTIVATE per 8 Tck is still OK down to 1.25 ns 54 Reads are in 16-byte colums: 1 8-burst (16 bytes) in a row, then next row, bank inc first. Then (if needed) - next column 55 Number of rows should be >=5 (4 now for tCK=2.5ns to meet tRP (precharge to activate) of the same bank (tRP=13ns) 56 Can read less if just one column 57 TODO: Maybe allow less rows with different sequence (no autoprecharge/no activate?) Will not work if row crosses page boundary 61 1: Most tile heights cause timing violation. Valid height mod 8 can be 0,6,7 (1,2,3,4,5 - invalid) 62 2: With option "keep_open" there should be no page boundary crossings, caller only checks the first line, and if window full width 63 is not multiple of CAS page, page crossings can appear on other than first line (fix caller to use largest common divider of page and 64 frame full width? Seems easy to fix 71 parameter CMD_DONE_BIT=
10,
// VDT BUG: CMD_DONE_BIT is used in a function call parameter! 77 // programming interface 83 input [
5:
0]
num_cols_in_m1,
// number of 16-pixel columns to read (rows first, then columns) - 1 86 input start,
// start generating commands 87 output reg [
31:
0]
enc_cmd,
// encoded command SuppressThisWarning VivadoSynthesis: [Synth 8-3332] Sequential element cmd_encod_tiled_rd.enc_cmd_reg[11:9,7:5,2] is unused and will be removed from module cmd_encod_tiled_rd. 88 output reg enc_wr,
// write encoded command 99 localparam ENC_CMD_SHIFT=
4;
// [5:4] - command: 0 -= NOP, 1 - READ, 2 - PRECHARGE, 3 - ACTIVATE 106 // localparam ENC_CMD_PRECHARGE=2; 107 localparam ENC_CMD_ACTIVATE=
2;
// using autoprecharge, so no PRECHARGE is needed. When en_act==0, ENC_CMD_ACTIVATE-> ENC_CMD_NOP (delay should be 0) 108 // localparam REPEAT_ADDR=3; 109 localparam LOOP_FIRST=
5;
// address of the first word in a loop 110 localparam LOOP_LAST=
6;
// address of the last word in a loop 111 localparam CMD_NOP=
0;
// 3-bit normal memory RCW commands (positive logic) 113 // localparam CMD_PRECHARGE=5; 115 // localparam AUTOPRECHARGE_BIT=COLADDR_NUMBER; 119 reg [
2:
0]
bank;
// memory bank; 122 // reg [FULL_ADDR_NUMBER-4:0] rowcol_inc; // increment {row.col} when bank rolls over, remove 3 LSBs (in 8-bursts) 128 // reg gen_run_d; // to output "done"? 138 reg [
FULL_ADDR_NUMBER-
4:
0]
top_rc;
// top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act 141 wire pre_act;
//1 cycle before optional ACTIVATE 143 reg [
5:
0]
scan_row;
// current row in a tile (valid @pre_act) 144 reg [
5:
0]
scan_col;
// current 16-byte column in a tile (valid @pre_act) 160 {
top_rc,
bank}:
// can not work if ACTIVATE is next after ACTIVATE in the last row (single-row tile) 167 // assign rom_cmd= rom_r[ENC_CMD_SHIFT+:2] & {enable_act,1'b1}; // disable bit 1 if activate is disabled (not the first column) 168 assign rom_cmd=
rom_r[
ENC_CMD_SHIFT+:
2];
// & {enable_act,1'b1}; // disable bit 1 if activate is disabled (not the first column) 181 always @ (
posedge clk)
begin 241 // ROM-based (registered output) encoded sequence 242 always @ (
posedge clk)
begin 261 always @ (
posedge clk)
begin 277 3'b0},
// [14:0] addr; // 15-bit row/column address 281 full_cmd[
2:
0],
// rcw; // RAS/CAS/WE, positive logic. full_cmd[0]==0 (never write/precharge) => enc_cmd_reg[11]==0 282 1'b0,
// odt_en; // enable ODT 283 1'b0,
// cke; // disable CKE 284 rom_r[
ENC_SEL],
// sel; // first/second half-cycle, other will be nop (cke+odt applicable to both) 285 1'b0,
// dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 286 1'b0,
// dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 287 1'b0,
// dqs_toggle; // enable toggle DQS according to the pattern 288 rom_r[
ENC_DCI],
// dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 289 rom_r[
ENC_BUF_WR],
// buf_wr; // connect to external buffer (but only if not paused) 290 1'b0,
// buf_rd; // connect to external buffer (but only if not paused) 291 rom_r[
ENC_NOP],
// nop; // add NOP after the current command, keep other data 293 else enc_cmd <=
func_encode_skip (
// encode pause 294 {{
CMD_PAUSE_BITS-
2{
1'b0}},
rom_skip[
1:
0]},
// skip; // number of extra cycles to skip (and keep all the other outputs) 295 pre_done,
// done, // end of sequence 296 3'b0,
// bank (here OK to be any) 297 1'b0,
// odt_en; // enable ODT 298 1'b0,
// cke; // disable CKE 299 rom_r[
ENC_SEL],
// sel; // first/second half-cycle, other will be nop (cke+odt applicable to both) 300 1'b0,
// dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 301 1'b0,
// dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 302 1'b0,
// dqs_toggle; // enable toggle DQS according to the pattern 303 rom_r[
ENC_DCI],
// dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 304 rom_r[
ENC_BUF_WR],
// buf_wr; // connect to external buffer (but only if not paused) 305 1'b0,
// buf_rd; // connect to external buffer (but only if not paused) 358 function [
31:
0]
func_encode_cmd;
359 input [
14:
0]
addr;
// 15-bit row/column address 360 input [
2:
0]
bank;
// bank (here OK to be any) 361 input [
2:
0]
rcw;
// RAS/CAS/WE, positive logic 362 input odt_en;
// enable ODT 363 input cke;
// disable CKE 364 input sel;
// first/second half-cycle, other will be nop (cke+odt applicable to both) 365 input dq_en;
// enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 366 input dqs_en;
// enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 367 input dqs_toggle;
// enable toggle DQS according to the pattern 368 input dci;
// DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 369 input buf_wr;
// connect to external buffer (but only if not paused) 370 input buf_rd;
// connect to external buffer (but only if not paused) 371 input nop;
// add NOP after the current command, keep other data 372 input buf_rst;
// connect to external buffer (but only if not paused) 375 addr[
14:
0],
// 15-bit row/column address 377 rcw[
2:
0],
// RAS/CAS/WE 378 odt_en,
// enable ODT 379 cke,
// may be optimized (removed from here)? 380 sel,
// first/second half-cycle, other will be nop (cke+odt applicable to both) 381 dq_en,
// enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 382 dqs_en,
// enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 383 dqs_toggle,
// enable toggle DQS according to the pattern 384 dci,
// DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 385 buf_wr,
// phy_buf_wr, // connect to external buffer (but only if not paused) 386 buf_rd,
// phy_buf_rd, // connect to external buffer (but only if not paused) 387 nop,
// add NOP after the current command, keep other data 388 buf_rst // Reserved for future use 393 function [
31:
0]
func_encode_skip;
394 input [
CMD_PAUSE_BITS-
1:
0]
skip;
// number of extra cycles to skip (and keep all the other outputs) 395 input done;
// end of sequence 396 input [
2:
0]
bank;
// bank (here OK to be any) 397 input odt_en;
// enable ODT 398 input cke;
// disable CKE 399 input sel;
// first/second half-cycle, other will be nop (cke+odt applicable to both) 400 input dq_en;
// enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 401 input dqs_en;
// enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 402 input dqs_toggle;
// enable toggle DQS according to the pattern 403 input dci;
// DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 404 input buf_wr;
// connect to external buffer (but only if not paused) 405 input buf_rd;
// connect to external buffer (but only if not paused) 406 input buf_rst;
// connect to external buffer (but only if not paused) 408 func_encode_skip=
func_encode_cmd (
410 bank[
2:
0],
// bank (here OK to be any) 411 3'b0,
// RAS/CAS/WE, positive logic 412 odt_en,
// enable ODT 414 sel,
// first/second half-cycle, other will be nop (cke+odt applicable to both) 415 dq_en,
// enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 416 dqs_en,
// enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 417 dqs_toggle,
// enable toggle DQS according to the pattern 418 dci,
// DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 419 buf_wr,
// connect to external buffer (but only if not paused) 420 buf_rd,
// connect to external buffer (but only if not paused)
4431col_bankwire[COLADDR_NUMBER-1:0]
4411rowcol_increg[FRAME_WIDTH_BITS:0]
4406rowreg[ADDRESS_NUMBER-1:0]
4416rom_rreg[ROM_WIDTH-1:0]
4387FULL_ADDR_NUMBERADDRESS_NUMBER+COLADDR_NUMBER
4407colreg[COLADDR_NUMBER-4:0]
4430row_col_bankreg[FULL_ADDR_NUMBER-1:0]
[FRAME_WIDTH_BITS:0] 4378rowcol_inc_in
4437row_col_bank_next_wwire[FULL_ADDR_NUMBER-1:0]
[COLADDR_NUMBER-4:0] 4377start_col
4410num_cols128_m1reg[5:0]
[ADDRESS_NUMBER-1:0] 4376start_row
4415gen_addrreg[ROM_DEPTH-1:0]
4435next_rowcol_wwire[ADDRESS_NUMBER+COLADDR_NUMBER-4:0]
4421top_rcreg[FULL_ADDR_NUMBER-4:0]