47 TODO Comments from cmd_encod_tiled_rd, update 48 Minimal ACTIVATE period =4 Tcm or 10ns, so maximal no-miss rate is Tck=1.25 ns (800 MHz) 49 Minimal window of 4 ACTIVATE pulses - 16 Tck or 40 (40 ns), so one ACTIVATE per 8 Tck is still OK down to 1.25 ns 50 Reads are in 16-byte colums: 1 8-burst (16 bytes) in a row, then next row, bank inc first. Then (if needed) - next column 51 Number of rows should be >=5 (4 now for tCK=2.5ns to meet tRP (precharge to activate) of the same bank (tRP=13ns) 52 Can read less if just one column 53 TODO: Maybe allow less rows with different sequence (no autoprecharge/no activate?) Will not work if row crosses page boundary 57 1: Most tile heights cause timing violation. Valid height mod 8 can be 0,6,7 (1,2,3,4,5 - invalid - wrong - that was for tile16 mode) 58 2: With option "keep_open" there should be no page boundary crossings, caller only checks the first line, and if window full width 59 is not multiple of CAS page, page crossings can appear on other than first line (fix caller to use largest common divider of page and 60 frame full width? Seems easy to fix 67 parameter CMD_DONE_BIT=
10,
// VDT BUG: CMD_DONE_BIT is used in a function call parameter! 69 parameter RSEL=
1'b1 // Late/early READ commands 73 // programming interface 79 input [
5:
0]
num_cols_in_m1,
// number of 32-pixel columns to read (rows first, then columns) - 1 80 //(for compatibility with cmd_encod_tiled, LSB will be ignored) 83 input start,
// start generating commands 84 output reg [
31:
0]
enc_cmd,
// encoded command SuppressThisWarning VivadoSynthesis: [Synth 8-3332] Sequential element cmd_encod_tiled_32_rd.enc_cmd_reg[11:9,7:5,2] is unused and will be removed from module cmd_encod_tiled_32_rd. 85 output reg enc_wr,
// write encoded command 96 localparam ENC_CMD_SHIFT=
4;
// [5:4] - command: 0 -= NOP, 1 - READ, 2 - PRECHARGE, 3 - ACTIVATE 103 // localparam ENC_CMD_PRECHARGE=2; 104 localparam ENC_CMD_ACTIVATE=
2;
// using autoprecharge, so no PRECHARGE is needed. When en_act==0, ENC_CMD_ACTIVATE-> ENC_CMD_NOP (delay should be 0) 105 // localparam REPEAT_ADDR=3; 106 localparam LOOP_FIRST=
4;
// address of the first word in a loop 107 localparam LOOP_LAST=
6;
// address of the last word in a loop 108 localparam CMD_NOP=
0;
// 3-bit normal memory RCW commands (positive logic) 110 // localparam CMD_PRECHARGE=5; 112 // localparam AUTOPRECHARGE_BIT=COLADDR_NUMBER; 115 reg [
COLADDR_NUMBER-
4:
0]
col;
// start memory column in 8-bursts SuppressThisWarning VivadoSynthesis: [Synth 8-3332] Sequential element cmd_encod_tiled_32_rd.col_reg[0] is unused and will be removed from module cmd_encod_tiled_32_rd. 116 reg [
2:
0]
bank;
// memory bank; 118 reg [
5:
0]
num_cols128_m2;
// number of r16-byte columns in a tile -2 (even columns) SuppressThisWarning VivadoSynthesis: [Synth 8-3332] Sequential element cmd_encod_tiled_32_rd.num_cols128_m2_reg[0] is unused and will be removed from module cmd_encod_tiled_32_rd. 119 // reg [FULL_ADDR_NUMBER-4:0] rowcol_inc; // increment {row.col} when bank rolls over, remove 3 LSBs (in 8-bursts) 125 // reg gen_run_d; // to output "done"? 135 reg [
FULL_ADDR_NUMBER-
4:
0]
top_rc;
// top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act 138 wire pre_act;
//1 cycle before optional ACTIVATE 140 reg [
5:
0]
scan_row;
// current row in a tile (valid @pre_act) 141 reg [
5:
0]
scan_col;
// current 16-byte column in a tile (valid @pre_act) SuppressThisWarning VivadoSynthesis: [Synth 8-3332] Sequential element cmd_encod_tiled_32_rd.scan_col_reg[0] is unused and will be removed from module cmd_encod_tiled_32_rd. 157 {
top_rc,
bank}:
// can not work if ACTIVATE is next after ACTIVATE in the last row (single-row tile) 164 // assign rom_cmd= rom_r[ENC_CMD_SHIFT+:2] & {enable_act,1'b1}; // disable bit 1 if activate is disabled (not the first column) 165 assign rom_cmd=
rom_r[
ENC_CMD_SHIFT+:
2];
// & {enable_act,1'b1}; // disable bit 1 if activate is disabled (not the first column) 178 always @ (
posedge clk)
begin 183 // if (rst) gen_run_d <= 0; 184 // else gen_run_d <= gen_run; 243 // ROM-based (registered output) encoded sequence 244 always @ (
posedge clk)
begin 245 if (
mrst)
rom_r <=
0;
// TODO: make mrst cause gen_addr = 4'hf? 259 // do not combine this NOP - ENC_CMD_READ + ENC_NOP enables autoprecharge 268 always @ (
posedge clk)
begin 277 // else if ((rom_cmd==0) || (rom_cmd[1] && !enable_act)) enc_cmd <= func_encode_skip ( // encode pause 285 3'b0},
// [14:0] addr; // 15-bit row/column address 289 full_cmd[
2:
0],
// rcw; // RAS/CAS/WE, positive logic. full_cmd[0]==0 (never write/precharge) => enc_cmd_reg[11]==0 290 1'b0,
// odt_en; // enable ODT 291 1'b0,
// cke; // disable CKE 292 rom_r[
ENC_SEL],
// sel; // first/second half-cycle, other will be nop (cke+odt applicable to both) 293 1'b0,
// dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 294 1'b0,
// dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 295 1'b0,
// dqs_toggle; // enable toggle DQS according to the pattern 296 rom_r[
ENC_DCI],
// dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 297 rom_r[
ENC_BUF_WR],
// buf_wr; // connect to external buffer (but only if not paused) 298 1'b0,
// buf_rd; // connect to external buffer (but only if not paused) 299 rom_r[
ENC_NOP],
// nop; // add NOP after the current command, keep other data 301 else enc_cmd <=
func_encode_skip (
// encode pause 302 {{
CMD_PAUSE_BITS-
2{
1'b0}},
rom_skip[
1:
0]},
// skip; // number of extra cycles to skip (and keep all the other outputs) 303 pre_done,
// done, // end of sequence 304 3'b0,
// bank (here OK to be any) 305 1'b0,
// odt_en; // enable ODT 306 1'b0,
// cke; // disable CKE 307 rom_r[
ENC_SEL],
// sel; // first/second half-cycle, other will be nop (cke+odt applicable to both) 308 1'b0,
// dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 309 1'b0,
// dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 310 1'b0,
// dqs_toggle; // enable toggle DQS according to the pattern 311 rom_r[
ENC_DCI],
// dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 312 rom_r[
ENC_BUF_WR],
// buf_wr; // connect to external buffer (but only if not paused) 313 1'b0,
// buf_rd; // connect to external buffer (but only if not paused) 366 function [
31:
0]
func_encode_cmd;
367 input [
14:
0]
addr;
// 15-bit row/column address 368 input [
2:
0]
bank;
// bank (here OK to be any) 369 input [
2:
0]
rcw;
// RAS/CAS/WE, positive logic 370 input odt_en;
// enable ODT 371 input cke;
// disable CKE 372 input sel;
// first/second half-cycle, other will be nop (cke+odt applicable to both) 373 input dq_en;
// enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 374 input dqs_en;
// enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 375 input dqs_toggle;
// enable toggle DQS according to the pattern 376 input dci;
// DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 377 input buf_wr;
// connect to external buffer (but only if not paused) 378 input buf_rd;
// connect to external buffer (but only if not paused) 379 input nop;
// add NOP after the current command, keep other data 380 input buf_rst;
// connect to external buffer (but only if not paused) 383 addr[
14:
0],
// 15-bit row/column address 385 rcw[
2:
0],
// RAS/CAS/WE 386 odt_en,
// enable ODT 387 cke,
// may be optimized (removed from here)? 388 sel,
// first/second half-cycle, other will be nop (cke+odt applicable to both) 389 dq_en,
// enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 390 dqs_en,
// enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 391 dqs_toggle,
// enable toggle DQS according to the pattern 392 dci,
// DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 393 buf_wr,
// phy_buf_wr, // connect to external buffer (but only if not paused) 394 buf_rd,
// phy_buf_rd, // connect to external buffer (but only if not paused) 395 nop,
// add NOP after the current command, keep other data 396 buf_rst // Reserved for future use 401 function [
31:
0]
func_encode_skip;
402 input [
CMD_PAUSE_BITS-
1:
0]
skip;
// number of extra cycles to skip (and keep all the other outputs) 403 input done;
// end of sequence 404 input [
2:
0]
bank;
// bank (here OK to be any) 405 input odt_en;
// enable ODT 406 input cke;
// disable CKE 407 input sel;
// first/second half-cycle, other will be nop (cke+odt applicable to both) 408 input dq_en;
// enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 409 input dqs_en;
// enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 410 input dqs_toggle;
// enable toggle DQS according to the pattern 411 input dci;
// DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 412 input buf_wr;
// connect to external buffer (but only if not paused) 413 input buf_rd;
// connect to external buffer (but only if not paused) 414 input buf_rst;
// connect to external buffer (but only if not paused) 416 func_encode_skip=
func_encode_cmd (
418 bank[
2:
0],
// bank (here OK to be any) 419 3'b0,
// RAS/CAS/WE, positive logic 420 odt_en,
// enable ODT 422 sel,
// first/second half-cycle, other will be nop (cke+odt applicable to both) 423 dq_en,
// enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 424 dqs_en,
// enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 425 dqs_toggle,
// enable toggle DQS according to the pattern 426 dci,
// DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 427 buf_wr,
// connect to external buffer (but only if not paused) 428 buf_rd,
// connect to external buffer (but only if not paused) 4138top_rcreg[FULL_ADDR_NUMBER-4:0]
4148col_bankwire[COLADDR_NUMBER-1:0]
4152next_rowcol_wwire[ADDRESS_NUMBER+COLADDR_NUMBER-4:0]
4123rowreg[ADDRESS_NUMBER-1:0]
4132gen_addrreg[ROM_DEPTH-1:0]
4154row_col_bank_next_wwire[FULL_ADDR_NUMBER-1:0]
4128rowcol_increg[FRAME_WIDTH_BITS:0]
4104FULL_ADDR_NUMBERADDRESS_NUMBER+COLADDR_NUMBER
[ADDRESS_NUMBER-1:0] 4093start_row
4127num_cols128_m2reg[5:0]
4147row_col_bankreg[FULL_ADDR_NUMBER-1:0]
4124colreg[COLADDR_NUMBER-4:0]
4133rom_rreg[ROM_WIDTH-1:0]
[COLADDR_NUMBER-4:0] 4094start_col
[FRAME_WIDTH_BITS:0] 4095rowcol_inc_in