clk_to_clk2x.v

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`timescale 1ns/1ps

module  clk_to_clk2x(
    input  clk,     // single rate clock
    input  clk2x,   // double rate clock, approximately posedge aligned to clk
    output clk_sync // approximately repeating clk, clocked @posedge clk2x - use as CE to transfer data
);

    reg r_clk =    0;
    reg r_nclk2x = 0;
    reg r_clk2x;
   
    assign clk_sync=r_clk2x;
    
    always @(posedge r_nclk2x or posedge clk) begin
        if (r_nclk2x) r_clk <= 0;
        else          r_clk <= 1;
    end   

    always @(negedge clk2x) r_nclk2x <= r_clk;
    always @(posedge clk2x) r_clk2x <= !r_nclk2x;

endmodule