44 input xclk,
// pixel clock, sync to incoming data 47 input [
4:
0]
dlen,
// input data width 48 input ds,
// input data valid 49 input flush_in,
// flush remaining data - should be after last ds. Also prepares for the next block 50 output [
31:
0]
d_out,
// outpt 32-bit data 51 output reg [
1:
0]
bytes_out,
// (0 means 4) valid with dv 52 output reg dv,
// output data valid 53 output reg flush_out // delayed flush in matching the data latency 60 reg [
DATA3_LEN-
1:
0]
data3;
// second stage of the barrel shifter/ output register 62 reg [
5:
0]
early_length;
// number of bits in the last word (mod 32) 63 reg [
5:
0]
dlen1;
// use for the stage 2, MSB - carry out 64 reg [
5:
0]
dlen2;
// use for the stege 3 66 reg [
31:
0]
dmask2_rom;
// data mask (sync with data2) - 1 use new data, 0 - use old data. Use small ROM? 68 reg [
1:
0]
stage;
// delayed ds or flush 75 always @ (
posedge xclk)
begin 96 // barrel shifter stage 1 (0/8/16/24) 105 // barrel shifter stage 2 (0/2/4/6) 149 // barrel shifter stage 3 (0/1), combined with output/hold register 157 // dv <= (ds_stage[1] && dlen2[5]) || (flush_stage[1] && !(|data3[DATA3_LEN-1 -: 32])); 158 // dv <= (ds_stage[1] && dlen1[5]) || (flush_stage[1] && !(|data3[DATA3_LEN-1 -: 32])); 159 // dv <= (ds_stage[0] && dlen1[5]) || (flush_stage[1] && !(|data3[DATA3_LEN-1 -: 32])); 161 // no difference in number of cells 162 // if (rst ) bytes_out <= 0; // if the dv was caused by 32 bits full - output 4 bytes 163 // else if (ds_stage[1]) bytes_out <= 0; // if the dv was caused by 32 bits full - output 4 bytes 164 if (
rst ||
ds_stage[
1])
bytes_out <=
0;
// if the dv was caused by 32 bits full - output 4 bytes 1278DATA2_LENDIN_LEN + 32 - 2
1279DATA3_LENDIN_LEN + 32 - 1
1281data2reg[DATA2_LEN-1:0]
1277DATA1_LENDIN_LEN + 32 - 8
1290pre_bits_out_wwire[4:0]
1282data3reg[DATA3_LEN-1:0]
1280data1reg[DATA1_LEN-1:0]