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00005 #ifndef _ASM_FPGACONF_H
00006 #define _ASM_FPGACONF_H
00007
00008
00009
00010 #define FPGACONF_IOCTYPE 129
00011
00012 #define FPGACONF_READREG 140 // read 32-bit register (through CSP0)
00013 #define FPGACONF_WRITEREG 141 // write 32-bit register (through CSP0)
00014 #define FPGACONF_READREG_L 142 // read lower 16 bits (through CSP0)
00015 #define FPGACONF_READREG_H 143 // read upper 16 bits (through CSP0)
00016 #define FPGACONF_READREG4 144 // read 32-bit register (through CSP4)
00017 #define FPGACONF_WRITEREG4 145 // write 32-bit register (through CSP4)
00018 #define FPGACONF_READREG_L4 146 // read lower 16 bits (through CSP4)
00019 #define FPGACONF_READREG_H4 147 // read upper 16 bits (through CSP4)
00020
00021 #define FPGACONF_GETSTATE 148 // read FPGA/clock state (minor FPGACONF_MINOR_IORW)
00022
00023 #define FPGACONF_RD_WAITSTATES 150 // read R_WAITSTATES
00024 #define FPGACONF_WR_WAITSTATES 151 // write R_WAITSTATES
00025
00026 #define FPGACONF_START_CAPTURE 152 // start capturing I/O pins to memory (IRQ off!). argument time 1=1ms (actually - longer)
00027 #define FPGACONF_READ_CAPTURE 153 // read captured I/O pins. 1-st time (after FPGACONF_START_CAPTURE) - length, after that - data
00028
00029 #define FPGACONF_CANON_IOBYTE 154 // write/read byte to CANON lens interface
00030
00031
00032 #define FPGA_STATE_LOADED 0x0000FFFF //
00033 #define FPGA_STATE_CLOCKS 0x000F0000 //
00034 #define FPGA_STATE_INITIALIZED 0x00F00000 //
00035 #define FPGA_STATE_SDRAM_INIT 0x00100000 //
00036
00037 #define FPGACONF_CONTROL_REG 155 // modify FPGA control register (0x10)
00038
00039 #define FPGACONF_CR_MODIFY 0x0e //(bit number)<<2 | op; op= 0 - nop, 1 - set, 2 - reset, 3 - toggle)
00040 #define FPGACONF_CR_SHADOW 0x0f
00041 #define FPGACONF_CR_SHADOW1 0x10
00042
00043
00044
00045
00046 #ifndef I2C_WRITEARG
00047 #define I2C_WRITEARG(bus, slave, reg, value) (((bus) << 24) | ((slave) << 16) | ((reg) << 8) | (value))
00048 #define I2C_READARG(bus, slave, reg) (((bus) << 24) | ((slave) << 16) | ((reg) << 8))
00049
00050 #define I2C_ARGBUS(arg) (((arg) >> 24) & 0x1)
00051 #define I2C_ARGSLAVE(arg) (((arg) >> 16) & 0xff)
00052 #define I2C_ARGREG(arg) (((arg) >> 8) & 0xff)
00053 #define I2C_ARGVALUE(arg) ((arg) & 0xff)
00054
00055 #define I2C_WRITEREG 0x1
00056 #define I2C_READREG 0x2
00057 #endif
00058
00059
00060
00061
00062
00063
00064 #define FPGA_PGM 0x3
00065 #define FPGA_STAT 0x4
00066 #define FPGA_JTAG 0x5
00067 #define FPGA_PA_RD 0x6
00068 #define FPGA_PA_WR 0x7
00069 #ifndef PGA_JTAG_ARG
00070 #define FPGA_JTAG_ARG(tms, len, d) (((tms) << 11) | ((len) << 8) | ((d) & 0xff))
00071 #define FPGA_JTAG_TMS(arg) ((arg >> 11) & 1)
00072 #define FPGA_JTAG_LEN(arg) ((arg >> 8) & 7)
00073 #define FPGA_JTAG_DW(arg) ( arg & 0xff)
00074 #endif
00075
00076 #define _FCCMD(x,y) (_IO(FPGACONF_IOCTYPE, (x << 6) | (y & 0x3f)))
00077
00078
00079
00080 #ifndef ERR_I2C_SCL_ST0
00081 #define ERR_I2C_SCL_ST0 1
00082 #define ERR_I2C_SDA_ST0 2
00083 #define ERR_I2C_SCL_ST1 4
00084 #define ERR_I2C_SDA_ST1 8
00085 #define ERR_I2C_SCL_NOPULLUP 16
00086 #define ERR_I2C_SDA_NOPULLUP 32
00087
00088 #define ERR_I2C_NOTDETECTED 64
00089 #define ERR_I2C_SHORT 128
00090 #define ERR_I2C_BSY 256
00091 #define ERR_I2C_NACK 512
00092 #endif
00093
00094
00095 #define IO_CSP0R0 0x10
00096 #define IO_CSP0W0 0x20
00097
00098 #define IO_CSP0R(a) (IO_CSP0R0 + a)
00099 #define IO_CSP0W(a) (IO_CSP0W0 + a)
00100
00101 #define IO_CSP0_R 1
00102 #define IO_CSP0_W 2
00103
00104 #endif
00105