os/linux-2.6-tag--devboard-R2_10-4/arch/cris/arch-v32/drivers/elphel/fpgaclocks.c

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/*!***************************************************************************
*! FILE NAME  : fpgaclocks353.c
*! provides control of the FPGA clocks based on 3-pll generator
*! Direct r/w of the CY22393 over the I2C interface (connected to PB.16 and PB.17 of the CPU)
*! supports 3 PLLs connected to 3 outputs (clk0, clk1 and clk2)
*! clk3 can be only turned on to Xtal frequency (12MHz) or off
*! Input parameter specifies frequency in Hz, internally data is rounded to 100Hz
*!
*!
*! Copyright (C) 2002-2006 Elphel, Inc.
*! -----------------------------------------------------------------------------**
*!
*!  This program is free software: you can redistribute it and/or modify
*!  it under the terms of the GNU General Public License as published by
*!  the Free Software Foundation, either version 3 of the License, or
*!  (at your option) any later version.
*!
*!  This program is distributed in the hope that it will be useful,
*!  but WITHOUT ANY WARRANTY; without even the implied warranty of
*!  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
*!  GNU General Public License for more details.
*!
*!  You should have received a copy of the GNU General Public License
*!  along with this program.  If not, see <http://www.gnu.org/licenses/>.
*! -----------------------------------------------------------------------------**
*!  $Log: fpgaclocks353.c,v $
*!  Revision 1.1.1.1  2008/11/27 20:04:00  elphel
*!
*!
*!  Revision 1.3  2008/09/22 22:55:48  elphel
*!  snapshot
*!
*!  Revision 1.2  2008/09/20 00:29:49  elphel
*!  moved driver major/minor numbers to a single file - include/asm-cris/elphel/driver_numbers.h
*!
*!  Revision 1.1.1.1  2007/08/17 10:23:18  elphel
*!  This is a fresh tree based on elphel353-2.10
*!
*!  Revision 1.7  2007/08/17 10:23:18  spectr_rain
*!  switch to GPL3 license
*!
*!  Revision 1.6  2007/07/20 10:17:45  spectr_rain
*!  *** empty log message ***
*!
*!  Revision 1.2  2007/06/28 02:23:49  elphel
*!  removed initilaization to some frequencies during Linux booting (they are programmed in other places)
*!
*!  Revision 1.1.1.1  2007/02/23 10:11:48  elphel
*!  initial import into CVS
*!
*!  Revision 1.2  2005/05/10 21:08:49  elphel
*!  *** empty log message ***
*!

*/

/****************** INCLUDE FILES SECTION ***********************************/
#include <linux/autoconf.h>

#include <linux/module.h>
#include <linux/sched.h>
#include <linux/slab.h>
   #include <linux/ioport.h> // needed?
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/string.h>
//#include <linux/poll.h>
#include <linux/init.h>

//#include <linux/interrupt.h>
//#include <linux/spinlock.h>


//#include <asm/svinto.h> - obsolete

// #include <asm/etraxgpio.h> // probably just for gpio driver
#include <asm/arch/hwregs/reg_map.h>
#include <asm/arch/hwregs/reg_rdwr.h>
#include <asm/arch/hwregs/gio_defs.h>
#include <asm/arch/hwregs/intr_vect_defs.h>
#include <asm/arch/hwregs/pinmux_defs.h>


#include <asm/io.h>
#include <asm/system.h>
#include <asm/irq.h>



#include <asm/delay.h>
#include <asm/uaccess.h>

#include <asm/elphel/driver_numbers.h>
#include <asm/elphel/fpgaconfa.h>
#include <asm/elphel/fpgaclocks.h>

#include "fpgactrl.h" // extern fpga_state

#define D(x)
//#define D(x) printk("%s:%d:",__FILE__,__LINE__);x
//#define D(x) x
#define D1(x)
//#define D1(x) printk("%s:%d:",__FILE__,__LINE__);x

#define D2(x)
//#define D2(x) x

#define D3(x)
//#define D3(x) printk("%s:%d:",__FILE__,__LINE__);x

// add to other drivers to use clock change function
//extern int setClockFreq(int nclock, int freq) { // freq now in Hz

//#define D5(x) printk("%s:%d:",__FILE__,__LINE__);x
#define D5(x)


//=========================
#define FPGA_CLOCK_DRIVER_NAME "Elphel (R) model 353 system clocks (PLL frequency synth.) driver"
#define FPGA_CLOCK_MAXMINOR 10




/****************** I2C DEFINITION SECTION *************************/
#define XCLOCK_LOW_TIME            8
#define XCLOCK_HIGH_TIME           8
#define XSTART_CONDITION_HOLD_TIME 8
#define XSTOP_CONDITION_HOLD_TIME  8
#define XENABLE_OUTPUT             0x01
#define XENABLE_INPUT              0x00
#define XI2C_CLOCK_HIGH            1
#define XI2C_CLOCK_LOW             0
#define XI2C_DATA_HIGH             1
#define XI2C_DATA_LOW              0
/*
port B:
 16 - I2C SDA
 17 - I2C SCL
*/

#define xi2c_delay(usecs) udelay(usecs)

static int clock_frequency[4]; // in Hz
typedef struct {
  unsigned int p :   11; // p - 16..1600
  unsigned int q :   8;  // q - 0.. 255
  unsigned int dv:   7;  // dv - 1.. 127
  unsigned int corr: 3;  // 0/1/2/3/4
  unsigned int rslt:   3;  // 0 - OK, 1 - frequency low, 2 - frequency high, 3 - other
} t_pll_params;
 

int xi2c_diagnose(void);
int   xi2c_start(void);
void xi2c_stop(void);
void xi2c_nostop(void);
int xi2c_outbyte(unsigned char d);
unsigned char xi2c_inbyte(void);
void xi2c_sendack(void);
int fi2c_writeData(unsigned char theSlave, unsigned char *theData, int size, int nostop);
int fi2c_readData(unsigned char theSlave, unsigned char *theData, int size);

int fi2c_ioctl(struct inode *inode, struct file *file,  unsigned int cmd, unsigned long arg);
int calc_pll_params (unsigned int f, t_pll_params * pars); // f -in Hz

int setCYField (int addr, int mask, int value);
int setClockFreq(int nclock, int freq); // freq now in Hz

// interface functions
static const char fpga_clock_name[] = "fpga_clock_control";
static int minors[FPGA_CLOCK_MAXMINOR+1]; // each minor can be opened only once
static int     fpga_clock_open   (struct inode *inode, struct file *filp);
static int     fpga_clock_release(struct inode *inode, struct file *filp);
static int     fpga_clock_ioctl  (struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg);
static int __init fpga_clock_init(void);


static struct file_operations fpga_clock_fops = {
  owner:    THIS_MODULE,
  open:     fpga_clock_open,
  release:  fpga_clock_release,
  ioctl:    fpga_clock_ioctl,
};





#define CY223933_SA 0xd2
// in Hz
#define CY22393_SCALE 100 // precision will be 100Hz
#define CY22393_PLLMIN (100000000/CY22393_SCALE)
#define CY22393_PLLMAX (400000000/CY22393_SCALE)
#define CY22393_XTAL   ( 12000000/CY22393_SCALE)
#define CY22393_OUTMAX (166000000/CY22393_SCALE)
#define CY22393_PMIN 16
#define CY22393_PMAX 1600


int calc_pll_params (unsigned int f, t_pll_params * pars) { // f -in Hz
//   t_pll_params pars;
   unsigned int f0= CY22393_XTAL;
   unsigned int f0_2= CY22393_XTAL/2;
   unsigned int fpmn= CY22393_XTAL * (CY22393_PMIN + 6);
   unsigned int fpmx= CY22393_XTAL * (CY22393_PMAX + 6);
   int divmn, divmx, err1,err, div,q,qmn,qmx,qmx1,fdv,p, e,fdvq;
   pars->rslt=3; // other error
   D(printk("f0=%d,f=%d, CY22393_OUTMAX=%d\r\n",f0,f,CY22393_OUTMAX));
   f/=CY22393_SCALE; // to fit into 32-bit calcualtions
   D(printk("f0=%d,f=%d, CY22393_OUTMAX=%d\r\n",f0,f,CY22393_OUTMAX));
   if (f>CY22393_OUTMAX) {
     pars->rslt=2;
     D(printk("f0=%d,f=%d, CY22393_OUTMAX=%d\r\n",f0,f,CY22393_OUTMAX));
     return pars->rslt;
   }
   if (f <=0 ) {
     pars->rslt=1;
     D(printk("f0=%d,f=%d, CY22393_OUTMAX=%d\r\n",f0,f,CY22393_OUTMAX));
     return pars->rslt;
   }
   divmx=CY22393_PLLMAX/f; if (divmx > 127) divmx=127; // could not be <1
   divmn=CY22393_PLLMIN/f; if (divmn < 1)   divmn=1;
   if (divmn >127) {
     pars->rslt=1;
     D(printk("f0=%d,f=%d, CY22393_OUTMAX=%d, divmn=%d\r\n",f0,f,CY22393_OUTMAX,divmn));
     return pars->rslt;
   }
   err1=f;
   qmx1=0;
   for (div=divmn;div<=divmx;div++) {
     err=err1*div;
     fdv=f*div;
     qmn=fpmn/fdv-2; if (qmn < 0) qmn=0;
     qmx=fpmx/fdv-2; if (qmx >255) qmx=255;
// recalculate qmn to avoid same div*qmn as already tried with lover div
     D1(printk("div=%d,qmn=%d, qmx=%d\r\n",div,qmn,qmx));
     if (div==1) qmx1=qmx;
     else if ((qmn*div) < qmx1) qmn=qmx1/div;
     for (q=qmn+2;q<=qmx+2; q++) {
       fdvq=fdv*q;
       p= (fdvq+f0_2)/f0; // can p be out of range here?
       e= fdvq-f0*p; if (e<0) e=-e;
       if (e< (err*q)) { // better solution found
         pars->rslt=0;
         pars->p=p-6;
         pars->q=q-2;
         pars->dv=div;
         err1=e/q/div;
         err=err1*div;
         D1(printk("f=%d, div=%d, p=%d,q=%d, err1=%d\r\n", (f0*p)/q/div, div,p, q, err1));
         if (err1==0) {
           pars->corr=(pars->p<226)?0:((pars->p<621)?1:((pars->p<829)?2:((pars->p<1038)?3:4)));
           D1(printk("f=%d, div=%d, p=%d,q=%d, err1=%d, rslt=%d\r\n",
           (f0*(pars->p+6))/(pars->q+2)/pars->dv,
           pars->dv,
           (pars->p+6),
           (pars->q+2),
           err1,
           pars->rslt));
           return pars->rslt;
         }
       }
     }
   }
   D1(printk("f=%d, div=%d, p=%d,q=%d, err1=%d, rslt=%d\r\n",
           (f0*(pars->p+6))/(pars->q+2)/pars->dv,
           pars->dv,
           (pars->p+6),
           (pars->q+2),
           err1,
           pars->rslt));
   pars->corr=(pars->p<226)?0:((pars->p<621)?1:((pars->p<829)?2:((pars->p<1038)?3:4)));
   return pars->rslt;
}






int setCYField (int addr, int mask, int value);

/* I2C functions */

#if 0
inline void xi2c_disable(void){
    reg_gio_rw_pb_dout      pb_dout=REG_RD(gio, regi_gio, rw_pb_dout);  
    reg_gio_rw_pb_oe        pb_oe =   REG_RD(gio, regi_gio, rw_pb_oe);
    pb_dout.data |=  0x20000;
    pb_oe.oe &= ~0x10000; //SDA - in 
    pb_oe.oe |=  0x20000; //SCL out
    REG_WR(gio, regi_gio, rw_pb_oe, pb_oe);
    REG_WR(gio, regi_gio, rw_pb_dout, pb_dout);
D2(printk("x"));
 }; // *R_PORT_PB_SET=(portb_shadow  = 0x0203)
inline void xi2c_dir_out(void){ // is it really needed (only in start)
    reg_gio_rw_pb_dout      pb_dout=REG_RD(gio, regi_gio, rw_pb_dout);  
    reg_gio_rw_pb_oe        pb_oe =   REG_RD(gio, regi_gio, rw_pb_oe);
    pb_dout.data |=  0x20000;
    pb_dout.data &= ~0x10000;
    pb_oe.oe     |=  0x30000; //SCL out, SDA out
    REG_WR(gio, regi_gio, rw_pb_oe, pb_oe);
    REG_WR(gio, regi_gio, rw_pb_dout, pb_dout);
D2(printk(">"));
}; // *R_PORT_PB_SET=(portb_shadow  = 0x0303)
inline void xi2c_dir_in(void){
    reg_gio_rw_pb_dout      pb_dout=REG_RD(gio, regi_gio, rw_pb_dout);  
    reg_gio_rw_pb_oe        pb_oe =   REG_RD(gio, regi_gio, rw_pb_oe);
    pb_dout.data |=  0x20000;
    pb_dout.data &= ~0x10000;
    pb_oe.oe &= ~0x10000; //SDA - in 
    pb_oe.oe |=  0x20000; //SCL out
    REG_WR(gio, regi_gio, rw_pb_oe, pb_oe);
    REG_WR(gio, regi_gio, rw_pb_dout, pb_dout);
D2(printk("<"));
}; //  *R_PORT_PB_SET=(portb_shadow  = 0x0203)
inline void xi2c_scl_0(void){
    reg_gio_rw_pb_dout      pb_dout=REG_RD(gio, regi_gio, rw_pb_dout);  
    pb_dout.data &= ~0x20000;
    REG_WR(gio, regi_gio, rw_pb_dout, pb_dout);
D2(printk("\\"));
}; //   *R_PORT_PB_SET=(portb_shadow &= 0x0301)
inline void xi2c_scl_1(void){
    reg_gio_rw_pb_dout      pb_dout=REG_RD(gio, regi_gio, rw_pb_dout);  
    pb_dout.data |= 0x20000;
    REG_WR(gio, regi_gio, rw_pb_dout, pb_dout);
D2(printk("/"));
}; //   *R_PORT_PB_SET=(portb_shadow |= 0x0002)
inline void xi2c_sda(int x){
/*
    reg_gio_rw_pb_dout      pb_dout=REG_RD(gio, regi_gio, rw_pb_dout);  
    pb_dout.data &= ~0x10000;
    pb_dout.data |= x? 0x10000:0;
    REG_WR(gio, regi_gio, rw_pb_dout, pb_dout);
*/
// add acceleration here ?

    reg_gio_rw_pb_oe        pb_oe =   REG_RD(gio, regi_gio, rw_pb_oe);
    if (x) pb_oe.oe     &= ~0x10000; //SDA disabled (1)
    else   pb_oe.oe     |= ~0x10000; //SDAenabled (0)

    REG_WR(gio, regi_gio, rw_pb_oe, pb_oe);

D2(printk("%d",x?1:0));
}; //  *R_PORT_PB_SET=(portb_shadow = (portb_shadow & 0x0002) | 0x0300 | ((x)? 1:0));
inline int  xi2c_getbit(void){
D2(printk("%c",(((REG_RD(gio, regi_gio, r_pb_din)).data)>>16) & 1?'H':'L'));
    return (((REG_RD(gio, regi_gio, r_pb_din)).data)>>16) & 1;
}; //  (*R_PORT_PB_READ & 1)
inline int  xi2c_getscl(void){
D2(printk("%c",(((REG_RD(gio, regi_gio, r_pb_din)).data)>>16) & 1?'+':'-'));
    return (((REG_RD(gio, regi_gio, r_pb_din)).data) >> 17) & 1;
}; //  ((*R_PORT_PB_READ >>1) & 1)


#endif


inline void xi2c_disable(void){ //initial condition, no fast pull up for data scl=1, sda=z (==1)
    reg_gio_rw_pb_dout      pb_dout=REG_RD(gio, regi_gio, rw_pb_dout);  
    reg_gio_rw_pb_oe        pb_oe =   REG_RD(gio, regi_gio, rw_pb_oe);
    pb_dout.data |=  0x30000;
    pb_oe.oe &=     ~0x10000; //SDA - in 
    pb_oe.oe |=      0x20000; //SCL out
    REG_WR(gio, regi_gio, rw_pb_oe, pb_oe);
    REG_WR(gio, regi_gio, rw_pb_dout, pb_dout);
D2(printk("x"));
 };

inline void xi2c_scl(int x){ // sst SCL line to x (oe supposed to be setup earlier)
    reg_gio_rw_pb_dout      pb_dout=REG_RD(gio, regi_gio, rw_pb_dout);  
    if (x) pb_dout.data |=  0x20000;
    else   pb_dout.data &= ~0x20000;
    REG_WR(gio, regi_gio, rw_pb_dout, pb_dout);
D2(if (x) printk("/"); else printk("\\"));
 }

inline void xi2c_sda (int x){ // sst SDA line to x (accelerate with active high)
    reg_gio_rw_pb_dout      pb_dout=REG_RD(gio, regi_gio, rw_pb_dout);  
    reg_gio_rw_pb_oe        pb_oe =   REG_RD(gio, regi_gio, rw_pb_oe);
    if (x) {
        pb_dout.data |=  0x10000; // SDA=1
        pb_oe.oe     |=  0x10000; // SDA out enable
        REG_WR(gio, regi_gio, rw_pb_dout, pb_dout);
        REG_WR(gio, regi_gio, rw_pb_oe, pb_oe);
        pb_oe.oe     &= ~0x10000; // SDA out disable
        D2(printk("1"));

    } else {
        pb_dout.data &= ~0x10000; // SDA=0
        pb_oe.oe     |=  0x10000; // SDA out enable
        REG_WR(gio, regi_gio, rw_pb_dout, pb_dout);
        REG_WR(gio, regi_gio, rw_pb_oe, pb_oe);
        D2(printk("0"));
    }
    REG_WR(gio, regi_gio, rw_pb_dout, pb_dout); // just extra delay
    REG_WR(gio, regi_gio, rw_pb_dout, pb_dout); // just extra delay
    REG_WR(gio, regi_gio, rw_pb_oe, pb_oe); // now - disable active pullup for SDA line (when sda=1, nop if sda=0)
 }

inline int  xi2c_getbit(void){
D2(printk("%c",(((REG_RD(gio, regi_gio, r_pb_din)).data)>>16) & 1?'H':'L'));
    return (((REG_RD(gio, regi_gio, r_pb_din)).data)>>16) & 1;
}; //  (*R_PORT_PB_READ & 1)
inline int  xi2c_getscl(void){
D2(printk("%c",(((REG_RD(gio, regi_gio, r_pb_din)).data)>>16) & 1?'+':'-'));
    return (((REG_RD(gio, regi_gio, r_pb_din)).data) >> 17) & 1;
}; //  ((*R_PORT_PB_READ >>1) & 1)

/*
inline void xi2c_disable(void);
inline void xi2c_scl(int x);
inline void xi2c_sda (int x);
inline int  xi2c_getbit(void);
inline int  xi2c_getscl(void);
*/



void initPortB(void) {
// connect 2 lower bits of port B to GPIO, disconnect from IOP
    unsigned long tmp;
    reg_pinmux_rw_pb_iop    pinmux_b_iop;
    reg_pinmux_rw_pb_gio    pinmux_b_gio;

    pinmux_b_iop= REG_RD(pinmux, regi_pinmux, rw_pb_iop);
    tmp = REG_TYPE_CONV(unsigned long, reg_pinmux_rw_pb_iop, pinmux_b_iop);
    tmp &= ~0x030000;
    pinmux_b_iop = REG_TYPE_CONV(reg_pinmux_rw_pb_iop, unsigned long, tmp);
    REG_WR(pinmux, regi_pinmux, rw_pb_iop, pinmux_b_iop);

    pinmux_b_gio= REG_RD(pinmux, regi_pinmux, rw_pb_gio);
    tmp = REG_TYPE_CONV(unsigned long, reg_pinmux_rw_pb_gio, pinmux_b_gio);
    tmp |=  0x030000;
    pinmux_b_gio = REG_TYPE_CONV(reg_pinmux_rw_pb_gio, unsigned long, tmp);
    REG_WR(pinmux, regi_pinmux, rw_pb_gio, pinmux_b_gio);
    xi2c_disable();
}

/* diagnose i2c bus problems. Will always return non-zero
Normally is called from xi2c_start, if it detects problem  */
int xi2c_diagnose(void) {
   int error=0;
  D(printk("diagnose\r\n"));

   while (!error) {
      xi2c_disable();xi2c_sda (1);  // will force high SCL, SDA
      xi2c_delay(XCLOCK_HIGH_TIME);
      if (!xi2c_getbit) error |= ERR_I2C_SDA_ST0;
      if (!xi2c_getscl) error |= ERR_I2C_SCL_ST0;
      if (error) break;
      xi2c_scl (0);
      xi2c_sda (0);
      xi2c_delay(XCLOCK_LOW_TIME);
      if (!xi2c_getbit) error |= ERR_I2C_SDA_ST0;
      if (!xi2c_getscl) error |= ERR_I2C_SCL_ST0;
      if (error) break;
      xi2c_disable(); // first disables, then sets high
      xi2c_delay(XCLOCK_HIGH_TIME*2);
      if (!xi2c_getbit) error |= ERR_I2C_SDA_NOPULLUP;
      if (!xi2c_getscl) error |= ERR_I2C_SCL_NOPULLUP;
      if (error) break;
      xi2c_sda(0);   // scl will be left disabled (high)
      if (!xi2c_getscl) error |= ERR_I2C_SHORT;
      break;
   }
   if (!error) error =   ERR_I2C_NOTDETECTED;
   /* try start-stop to reset effects of playing with sda/scl lines */
   xi2c_disable();  // will force high SCL, SDA
   xi2c_sda (0);
   xi2c_delay(XSTART_CONDITION_HOLD_TIME);
   xi2c_scl(0);
   xi2c_delay(XCLOCK_LOW_TIME*2);
   xi2c_scl(1);
   xi2c_delay(XCLOCK_HIGH_TIME*2);
   xi2c_sda (1);
   xi2c_delay(XSTOP_CONDITION_HOLD_TIME);
   xi2c_disable();
   return error;
}

/* generate i2c start condition and test bus */

int   xi2c_start(void) {
// int error=0;
   int i;
  D(for(i=0;i<300;i++) udelay(1000); printk("start:\r\n"); for(i=0;i<300;i++) udelay(1000));
   /* SCL=1 SDA=1 */
   xi2c_disable();  // will set high SCL, SDA
   xi2c_delay(XCLOCK_HIGH_TIME/2);
   /* if the periferial (?) driving sda low (after being interrupted)? - try to recover */
//   xi2c_dir_in();
   xi2c_delay(XCLOCK_HIGH_TIME/2);
   if (!xi2c_getbit()) {
      for (i=0;(i<9) && !xi2c_getbit();i++) {
         xi2c_scl(0);
         xi2c_delay(XCLOCK_LOW_TIME);
         xi2c_scl(1);
         xi2c_delay(XCLOCK_HIGH_TIME);
      }
      if (!xi2c_getbit) return  xi2c_diagnose(); // did not help - really stuck
      /* it is breathing - try "START"-"STOP" */
      xi2c_sda (0);
      xi2c_delay(XSTART_CONDITION_HOLD_TIME);
      xi2c_scl(0);
      xi2c_delay(XCLOCK_LOW_TIME*2);
      xi2c_scl(1);
      xi2c_delay(XCLOCK_HIGH_TIME*2);
      xi2c_sda (1);
      xi2c_delay(XSTOP_CONDITION_HOLD_TIME);
   }
   /* SCL=1 SDA=1 */
   xi2c_delay(XCLOCK_HIGH_TIME/2);
   if ((!xi2c_getbit()) || (!xi2c_getscl())) return  xi2c_diagnose();
   /* SCL=1 SDA=0 */
   xi2c_sda(0);
   xi2c_delay(XSTART_CONDITION_HOLD_TIME);
   if (( xi2c_getbit()) || (!xi2c_getscl())) return  xi2c_diagnose();
   /* SCL=0 SDA=0 */
   xi2c_scl(0);
   xi2c_delay(XCLOCK_LOW_TIME);
   if (( xi2c_getbit()) || ( xi2c_getscl())) return  xi2c_diagnose();
   return 0;
}

/* generate i2c stop condition */
void xi2c_stop(void) {  // assumed to be enabled
   /* SCL=0 SDA=0  */
  D(int i;)
  D( for (i=0;i<300;i++) udelay(1000); printk("stop:\r\n"); for(i=0;i<300;i++) udelay(1000));

   xi2c_scl (0);
   xi2c_sda (0);
   xi2c_delay(XCLOCK_LOW_TIME*2);
   /* SCL=1 SDA=0 */
   xi2c_scl(1);
   xi2c_delay(XCLOCK_HIGH_TIME*2);
   /* SCL=1 SDA=1 */
   xi2c_sda (1);
   xi2c_delay(XSTOP_CONDITION_HOLD_TIME);
//   xi2c_disable();  // both high with resistor pull-up
}

/* generate i2c "no-stop" condition before repeated start */
void xi2c_nostop(void) {  // assumed to be enabled
   /* SCL=0 SDA=0  */
  D(int i;)
  D( for (i=0;i<300;i++) udelay(1000); printk("nostop:\r\n"); for(i=0;i<300;i++) udelay(1000));

   xi2c_scl (0);
   xi2c_sda (0);
   xi2c_delay(XCLOCK_LOW_TIME*2);
   /* SCL=0 SDA=1 */
   xi2c_sda (1);
   xi2c_delay(XCLOCK_HIGH_TIME*2);
   /* SCL=1 SDA=1 */
   xi2c_scl(1);
   xi2c_delay(XSTOP_CONDITION_HOLD_TIME);
   xi2c_disable();  // both high with resistor pull-up
}




/* write a byte to the i2c interface , return acknowledge */
int xi2c_outbyte(unsigned char d) { 
   int i;
   unsigned char x=d;   // make it non-destructive
  D(printk("outbyte: byte=%x\r\n",  (int) x));

   for (i = 0; i < 8; i++) { // assumed to be with SCL=0;
      xi2c_sda (x & 0x80); // checks only on non-zero, so no need to '>>'
//portb_shadow
//  D(printk("%x ",  (int) portb_shadow));

      xi2c_delay(XCLOCK_LOW_TIME/2);
      xi2c_scl (1);
      xi2c_delay(XCLOCK_HIGH_TIME);
      xi2c_scl (0);
      xi2c_delay(XCLOCK_LOW_TIME/2);
      x <<= 1;
   }
  D(printk("  "));

   /* enable input    */
//   xi2c_dir_in();
   xi2c_sda (1);
   xi2c_delay(XCLOCK_LOW_TIME/2);
   xi2c_scl (1);
   xi2c_delay(XCLOCK_HIGH_TIME);
   i= (1-xi2c_getbit());
   xi2c_scl (0);
   xi2c_delay(XCLOCK_LOW_TIME/2);
  D(printk("ACK=%x ", i));


   return i;
}

/* read a byte from the i2c interface */

unsigned char xi2c_inbyte(void) { // assumed SCL=0, SDA=X
   unsigned char aBitByte = 0;
   int i;
   /* enable input */
  D(printk("inbyte: "));

//   xi2c_dir_in();
   xi2c_sda (1);
   /* get bits  */
   for (i = 0; i < 8; i++) {
      xi2c_delay(XCLOCK_LOW_TIME/2);
      /* low clock period   */
      xi2c_scl (1);
      xi2c_delay(XCLOCK_HIGH_TIME);
      aBitByte = (aBitByte << 1) | xi2c_getbit();
      xi2c_scl (0);
      xi2c_delay(XCLOCK_LOW_TIME/2);
   }
  D(printk(" data=%x\r\n", aBitByte));
   return aBitByte;  // returns with SCL=0, SDA - OFF
}

/*#---------------------------------------------------------------------------
*#
*# FUNCTION NAME: I2C::sendAck
*#
*# DESCRIPTION  : Send ACK on received data
*#
*#--------------------------------------------------------------------------*/
void xi2c_sendack(void) {
    D(printk("sendack\r\n"));

      xi2c_sda (0);
      xi2c_delay(XCLOCK_LOW_TIME/2);
      xi2c_scl (1);
      xi2c_delay(XCLOCK_HIGH_TIME);
      xi2c_scl (0);
      xi2c_delay(XCLOCK_LOW_TIME/2);
}

/*#---------------------------------------------------------------------------
*#
*# FUNCTION NAME: fi2c_writeData
*#
*# DESCRIPTION  : Writes a sequence of bytes to an I2C device
*# removed retries, will add test-ready later as a separate function
*# removed all "dummy stuff" - I never needed that
*#
*#--------------------------------------------------------------------------*/
int fi2c_writeData(unsigned char theSlave, unsigned char *theData, int size, int nostop) {
   int i,error=0;
   /* we don't like to be interrupted  *** WHY??? ***     */
   D3(printk("i2c_writeData:  theSlave=%x data=%x %x size=%x\r\n", theSlave, theData[0], theData[1], size));
   D(printk("writeData: %x %x %x %x\r\n", theSlave, theData[0], theData[1], size));

   /* generate start condition, test bus */
   if ((error=xi2c_start())) return error;
   /* send slave address, wait for ack */
   if(!xi2c_outbyte(theSlave)) {
       xi2c_stop();
       return ERR_I2C_BSY; // device does not exist or not ready
   }
// OK, now send theData verifying ACK goes after each byte
   for (i=0;i<size;i++) {
      if(!xi2c_outbyte(theData[i])) {
         xi2c_stop();
         return ERR_I2C_NACK; // device failure
      }
   }
   if (nostop) xi2c_nostop();
   else xi2c_stop();
   return 0;
}




/*#---------------------------------------------------------------------------
*#
*# FUNCTION NAME: i2c_readData
*#
*# DESCRIPTION  : Reads a data from the i2c device, returns 0- OK, else - error code
*#
*#--------------------------------------------------------------------------*/

int fi2c_readData(unsigned char theSlave, unsigned char *theData, int size) {
   int i, error=0;
   if ((error=xi2c_start())) return error;
   /* send slave address, wait for ack */
   D3(printk("i2c_readData:  theSlave=%x size=%x\r\n", theSlave, size));
   D(printk("readData:  %x %x\r\n", theSlave, size));

   if(!xi2c_outbyte(theSlave)) {
       xi2c_stop();
       return ERR_I2C_BSY; // device does not exist or not ready
   }
   for (i=0;i<size;i++) {
      theData[i]=xi2c_inbyte();
      xi2c_sendack();
   }
    xi2c_stop();
    return 0;
   
}






// for now - single register read/write only
int fi2c_ioctl(struct inode *inode, struct file *file,
     unsigned int cmd, unsigned long arg) {
//     unsigned char data[2];
     unsigned char data[10]; // for test purposes

     int error=0;
   D3(printk("i2c_ioctl cmd= %x, arg= %x\n\r",cmd,(int) arg));
   D3(printk("i2c_ioctl:  ((int *)file->private_data)[0]= %x\n\r",((int *)file->private_data)[0]));
   if(_IOC_TYPE(cmd) !=FPGA_CLOCK_IOCTYPE) {
      return -EINVAL;
   }

   switch (_IOC_NR(cmd)) {
      case FPGA_CLOCK_I2C_WRITEREG:

         /* write to an i2c slave */
         D3(printk("i2cw slave=%d, reg=%d, value=%d\n", 
             (int) I2C_ARGSLAVE(arg),
             (int) I2C_ARGREG(arg),
             (int) I2C_ARGVALUE(arg)));
         data[0]=I2C_ARGREG(arg);
         data[1]=I2C_ARGVALUE(arg);
         return -fi2c_writeData(I2C_ARGSLAVE(arg) & 0xfe, &data[0], 2,0); // stop at the end
      case FPGA_CLOCK_I2C_READREG:
      {
         /* read from an i2c slave */
         D3(printk("i2cr slave=%d, reg=%d ", 
             (int) I2C_ARGSLAVE(arg),
             (int) I2C_ARGREG(arg)));

         data[0]=I2C_ARGREG(arg);
         error=fi2c_writeData(I2C_ARGSLAVE(arg) & 0xfe, &data[0], 1,1); // nostop at the end
         if (error) return -error;

//         error=fi2c_readData(I2C_ARGSLAVE(arg) | 0x01, &data[1], 1);
         error=fi2c_readData(I2C_ARGSLAVE(arg) | 0x01, &data[1], 8); // just testing
         if (error) return -error;
         D3(printk("returned %d\n", data[1]));

         return data[1];
      }
      default:
         return -EINVAL;

   }
   return 0;
}


int setCYField (int addr, int mask, int value) {
    unsigned char data[2];
    int error;
    data[0]=addr;
    error=fi2c_writeData(CY223933_SA,       &data[0], 1, 1); // nostop
    if (error) return -error;
    error=fi2c_readData(CY223933_SA | 0x01, &data[1], 1);
    if (error) return -error;
    data[1]^=(data[1] ^ (unsigned long) value) & (unsigned long) mask;
    error=fi2c_writeData(CY223933_SA,       &data[0], 2, 0); // stop
    return error;
}

int getClockFreq(int nclock) {
  if ((nclock <0) || (nclock >3)) return -1; // bad clock number
  else return clock_frequency[nclock];
}
//TODO: add one more clock 
int setClockFreq(int nclock, int freq) { // freq now in Hz
  t_pll_params  pll_params;
  int i,bp,bq,bdiv,pllc,fact;
  bp=0; bq=0; bdiv=0; pllc= 0; // just to make gcc happy
  fact=0;
  D5(printk("setClockFreq(%d,%d)\r\n",nclock,freq));
  if ((freq!=0) && (nclock!=3) ){
    if ( (i=calc_pll_params (freq, &pll_params)) !=0) {
      printk("bad frequency for clock %d - %d Hz, err=%d\n",nclock,freq,i);
      return -2;
    }
    fact=CY22393_SCALE*(CY22393_XTAL*(pll_params.p+6)/(pll_params.q+2)/pll_params.dv);
    bp=  pll_params.p;    // (freqtab[freq]>>20)&0x7ff;
    bq=  pll_params.q;    // (freqtab[freq]>>12)&0xff;
    bdiv=pll_params.dv;   // (freqtab[freq]>> 4)&0xff;
    pllc=pll_params.corr; // freqtab[freq]     &0x0f;

//    printk ("fpgaclocks353.c::setClockFreq(clock=%d, freq=%d) bp=0x%x, bq=0x%x, bdiv=0x%x, pllc=0x%x\r\n", nclock, freq,bp,bq,bdiv,pllc);
  }
  switch (nclock) {
       case 0: 
          if (freq==0) {
            setCYField (0x16, 0x40, 0x00); // turn off pll3
            setCYField (0x09, 0x7f, 0x00); // turn off divider- A
            setCYField (0x08, 0x7f, 0x00); // turn off divider- A
          } else {
          setCYField (0x16, 0x7f, 0x40+(pllc<<3)+((bp & 1)<<2)+((bp & 0x600)>>9) );
          setCYField (0x15, 0xff, ((bp & 0x1fe)>>1) );
          setCYField (0x14, 0xff, bq );
          setCYField (0x09, 0x7f, bdiv); // set divider- A
          setCYField (0x08, 0x7f, bdiv); // set divider- A
          setCYField (0x0e, 0x03, 0x03); // set PLL3 as source for ClkA
          }
          fpga_state |= FPGA_STATE_CLOCKS;
          break;
       case 1:
          if (freq==0) {
            setCYField (0x0b, 0x7f, 0x00); // turn off divider- B
            setCYField (0x0a, 0x7f, 0x00); // turn off divider- B
            for (i=0;i<24;i+=3) setCYField (0x42+i, 0x40, 0x00); // turn off pll1
          } else {
// progam all variants
            for (i=0;i<24;i+=3) {
              setCYField (0x42+i, 0x7f, 0x40+(pllc<<3)+((bp & 1)<<2)+((bp & 0x600)>>9) );
              setCYField (0x41+i, 0xff, ((bp & 0x1fe)>>1) );
              setCYField (0x40+i, 0xff, bq );
            }
            setCYField (0x0b, 0x7f, bdiv); // set divider- B
            setCYField (0x0a, 0x7f, bdiv); // set divider- B
            setCYField (0x0e, 0x0c, 0x04); // set PLL1 as source for ClkB
          }
          break;
       case 2:
          if (freq==0) {
            setCYField (0x13, 0x40, 0x00); // turn off pll2
            setCYField (0x0d, 0x7f, 0x00); // turn off divider- D
          } else {
            setCYField (0x13, 0x7f, 0x40+(pllc<<3)+((bp & 1)<<2)+((bp & 0x600)>>9) );
            setCYField (0x12, 0xff, ((bp & 0x1fe)>>1) );
            setCYField (0x11, 0xff, bq );
            setCYField (0x0d, 0x7f, bdiv); // set divider- D
            setCYField (0x0e, 0xc0, 0x80); // set PLL2 as source for ClkD
          }
          break;
       case 3: 
         if ((freq!=0) && (freq!=CY22393_SCALE*CY22393_XTAL)) {
            printk("Only frequency 0 (off) and %d Hz (xtal) are allowed for channel 3\r\n",CY22393_SCALE*CY22393_XTAL);
            return -2;
          } else {
//  int setCYField (int devfd, int addr, int mask, int value) O_RDWR
            if (freq==0) {
              setCYField (0x0f, 0x04, 0x00); 
            } else {
              setCYField (0x0f, 0x04, 0x04); 
              fact= CY22393_SCALE*CY22393_XTAL;
            }
          }
          break;
       default: return -1; // wrong clock number
  }
  D5(printk("nclock=%d fact=%d\n",nclock,fact));
  clock_frequency[nclock]=fact;
  return fact;
}



//==============================================================================================================

//============================= driver interface =========================

static int fpga_clock_open(struct inode *inode, struct file *filp) {
   int p;
   p = MINOR(inode->i_rdev);
   D(printk("fpga_clock_open: minor=%x\r\n",p) );
   D(printk("filp=%lx\r\n",(unsigned long)filp) );
   switch ( p ) {
     case FPGA_CLOCK_MINOR_I2C :
     case FPGA_CLOCK_MINOR_CLOCKS :
      {
         if (minors[p])  return -EACCES;
         break;
      }
     default: return -EINVAL;
   }
   minors[p]=p;
   filp->private_data = &minors[p];
   return 0;
}

static int fpga_clock_release(struct inode *inode, struct file *filp) {
   int p = MINOR(inode->i_rdev);
   D(printk("fpga_clock_release:  done\r\n"));
   minors[p]=0;
   return 0;
}

static int fpga_clock_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) {// switch by minor

   int res=0;
   D(printk("fpga_clock_ioctl cmd= %x, arg= %x\n\r",cmd,(int) arg));
   D5(printk("fpga_clock_ioctl cmd= %x, arg= %x, _IOC_TYPE(cmd)=%x, nclock=%x\n\r",cmd,(int) arg, (int) _IOC_TYPE(cmd), (int) (_IOC_NR(cmd) & 7)));

     switch (((int *)filp->private_data)[0]) {

       case FPGA_CLOCK_MINOR_I2C : 
           {
             res=fi2c_ioctl (inode, filp, cmd, arg);
             return res;
           }
       case FPGA_CLOCK_MINOR_CLOCKS : 
           {
             if(_IOC_TYPE(cmd) ==FPGA_CLOCK_IOCTYPE_RD)   return getClockFreq(_IOC_NR(cmd) & 7);
             else if(_IOC_TYPE(cmd) !=FPGA_CLOCK_IOCTYPE) return -EINVAL;
             res=setClockFreq(_IOC_NR(cmd) & 7, arg); //clock number, value in Hz
             if (res<0) return -EINVAL;
             else return res; // actual frequency  
           }
     default:return -EINVAL;
     }
}

//

static int __init fpga_clock_init(void) {
   int i,res;
   res = register_chrdev(FPGA_CLOCK_MAJOR, fpga_clock_name, &fpga_clock_fops);
   if(res < 0) {
     printk(KERN_ERR "\nfpga_clock_init: couldn't get a major number %d.\n", FPGA_CLOCK_MAJOR);
     return res;
   }
   printk(FPGA_CLOCK_DRIVER_NAME" - %d\n",FPGA_CLOCK_MAJOR);
   for (i=0;i<=FPGA_CLOCK_MAXMINOR;i++) minors[i]=0;
   initPortB();
// Will initialize clocks in initscript
//   setClockFreq(0, 125000000);
//   setClockFreq(1,  20000000);
   fpga_state |= 0x10000; //mask 0xf0000
   return 0;
}



/* this makes sure that fpga_init is called during boot */

module_init(fpga_clock_init);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Andrey Filippov <andrey@elphel.com>.");
MODULE_DESCRIPTION(FPGA_CLOCK_DRIVER_NAME);

---