This is the complete list of members for huffman393, including all inherited members.

EXTRA_DLY	pulse_cross_clock	Parameter
rst	pulse_cross_clock	Input
src_clk	pulse_cross_clock	Input
dst_clk	pulse_cross_clock	Input
in_pulse	pulse_cross_clock	Input
out_pulse	pulse_cross_clock	Output
busy	pulse_cross_clock	Output
EXTRA_DLY_SAFE	pulse_cross_clock	Parameter
in_reg	pulse_cross_clock	Signal
out_reg	pulse_cross_clock	Signal
busy_r	pulse_cross_clock	Signal
MODE_16_BITS	table_ad_receive	Parameter
NUM_CHN	table_ad_receive	Parameter
clk	table_ad_receive	Input
a_not_d	table_ad_receive	Input
ser_d	table_ad_receive	Input
dv	table_ad_receive	Input
ta	table_ad_receive	Output
td	table_ad_receive	Output
twe	table_ad_receive	Output
addr_r	table_ad_receive	Signal
twe_r	table_ad_receive	Signal
td_r	table_ad_receive	Signal
WIDTH	latch_g_ce	Parameter
INIT	latch_g_ce	Parameter
IS_CLR_INVERTED	latch_g_ce	Parameter
IS_G_INVERTED	latch_g_ce	Parameter
rst	latch_g_ce	Input
g	latch_g_ce	Input
ce	latch_g_ce	Input
d_in	latch_g_ce	Input
q_out	latch_g_ce	Output
REGISTERS	ram18_var_w_var_r	Parameter
LOG2WIDTH_WR	ram18_var_w_var_r	Parameter
LOG2WIDTH_RD	ram18_var_w_var_r	Parameter
11587	ram18_var_w_var_r	Parameter
rclk	ram18_var_w_var_r	Input
raddr	ram18_var_w_var_r	Input
ren	ram18_var_w_var_r	Input
regen	ram18_var_w_var_r	Input
data_out	ram18_var_w_var_r	Output
wclk	ram18_var_w_var_r	Input
waddr	ram18_var_w_var_r	Input
we	ram18_var_w_var_r	Input
web	ram18_var_w_var_r	Input
data_in	ram18_var_w_var_r	Input
11598	ram18_32w_32r	Parameter
rclk	ram18_32w_32r	Input
raddr	ram18_32w_32r	Input
ren	ram18_32w_32r	Input
regen	ram18_32w_32r	Input
data_out	ram18_32w_32r	Output
wclk	ram18_32w_32r	Input
waddr	ram18_32w_32r	Input
we	ram18_32w_32r	Input
web	ram18_32w_32r	Input
data_in	ram18_32w_32r	Input
PWIDTH_WR	ram18_32w_32r	Parameter
PWIDTH_RD	ram18_32w_32r	Parameter
REGISTERS	ram18_lt32w_lt32r	Parameter
LOG2WIDTH_WR	ram18_lt32w_lt32r	Parameter
11613	ram18_lt32w_lt32r	Parameter
rclk	ram18_lt32w_lt32r	Input
raddr	ram18_lt32w_lt32r	Input
ren	ram18_lt32w_lt32r	Input
regen	ram18_lt32w_lt32r	Input
data_out	ram18_lt32w_lt32r	Output
wclk	ram18_lt32w_lt32r	Input
waddr	ram18_lt32w_lt32r	Input
we	ram18_lt32w_lt32r	Input
web	ram18_lt32w_lt32r	Input
data_in	ram18_lt32w_lt32r	Input
PWIDTH_WR	ram18_lt32w_lt32r	Parameter
PWIDTH_RD	ram18_lt32w_lt32r	Parameter
WIDTH_WR	ram18_lt32w_lt32r	Parameter
WIDTH_RD	ram18_lt32w_lt32r	Parameter
data_out16	ram18_lt32w_lt32r	Signal
data_in_ext	ram18_lt32w_lt32r	Signal
data_in16	ram18_lt32w_lt32r	Signal
REGISTERS	ram18_lt32w_32r	Parameter
11632	ram18_lt32w_32r	Parameter
rclk	ram18_lt32w_32r	Input
raddr	ram18_lt32w_32r	Input
ren	ram18_lt32w_32r	Input
regen	ram18_lt32w_32r	Input
data_out	ram18_lt32w_32r	Output
wclk	ram18_lt32w_32r	Input
waddr	ram18_lt32w_32r	Input
we	ram18_lt32w_32r	Input
web	ram18_lt32w_32r	Input
data_in	ram18_lt32w_32r	Input
PWIDTH_WR	ram18_lt32w_32r	Parameter
PWIDTH_RD	ram18_lt32w_32r	Parameter
WIDTH_WR	ram18_lt32w_32r	Parameter
data_in_ext	ram18_lt32w_32r	Signal
data_in16	ram18_lt32w_32r	Signal
REGISTERS	ram18_32w_lt32r	Parameter
11649	ram18_32w_lt32r	Parameter
rclk	ram18_32w_lt32r	Input
raddr	ram18_32w_lt32r	Input
ren	ram18_32w_lt32r	Input
regen	ram18_32w_lt32r	Input
data_out	ram18_32w_lt32r	Output
wclk	ram18_32w_lt32r	Input
waddr	ram18_32w_lt32r	Input
we	ram18_32w_lt32r	Input
web	ram18_32w_lt32r	Input
data_in	ram18_32w_lt32r	Input
PWIDTH_WR	ram18_32w_lt32r	Parameter
PWIDTH_RD	ram18_32w_lt32r	Parameter
WIDTH_RD	ram18_32w_lt32r	Parameter
data_out16	ram18_32w_lt32r	Signal
LOG2WIDTH_RD	ram18_dummy	Parameter
data_out	ram18_dummy	Output
xclk	huff_fifo393	Input
xclk2x	huff_fifo393	Input
en	huff_fifo393	Input
di	huff_fifo393	Input
ds	huff_fifo393	Input
want_read	huff_fifo393	Input
dav	huff_fifo393	Output
q	huff_fifo393	Output
wa	huff_fifo393	Signal
ra_r	huff_fifo393	Signal
fifo_o	huff_fifo393	Signal
ds1	huff_fifo393	Signal
synci	huff_fifo393	Signal
synco	huff_fifo393	Signal
sync_we	huff_fifo393	Signal
en2x	huff_fifo393	Signal
diff_a	huff_fifo393	Signal
re	huff_fifo393	Signal
nempty_r	huff_fifo393	Signal
nempty	huff_fifo393	Signal
many	huff_fifo393	Signal
xclk	huffman393
xclk2x	huffman393
en	huffman393
mclk	huffman393
tser_we	huffman393
tser_a_not_d	huffman393
tser_d	huffman393
di	huffman393
ds	huffman393
rdy	huffman393
do	huffman393
dl	huffman393
dv	huffman393
flush	huffman393
last_block	huffman393
test_lbw	huffman393
gotLastBlock	huffman393
clk_flush	huffman393
flush_clk	huffman393
fifo_or_full	huffman393
hcode_latch	huffman393
hlen_latch	huffman393
haddr70_latch	huffman393
haddr8_latch	huffman393
tables_re_latch	huffman393
tables_out	huffman393
haddr_r	huffman393
haddr_next	huffman393
haddr	huffman393
fifo_o	huffman393
stuffer_was_rdy	huffman393
read_next	huffman393
steps	huffman393
rll	huffman393
rll1	huffman393
rll2	huffman393
typeDC	huffman393
typeAC	huffman393
sval	huffman393
code_typ0	huffman393
tbsel_YC0	huffman393
code_typ1	huffman393
code_typ2	huffman393
code_typ3	huffman393
code_typ4	huffman393
tbsel_YC1	huffman393
tbsel_YC2	huffman393
tbsel_YC3	huffman393
out_bits	huffman393
out_len	huffman393
will_read	huffman393
var_do	huffman393
var_dl	huffman393
var_dl_late	huffman393
dv0	huffman393
eob	huffman393
gotDC	huffman393
gotAC	huffman393
gotRLL	huffman393
gotEOB	huffman393
gotLastWord	huffman393
gotColor	huffman393
want_read	huffman393
ready_to_flush	huffman393
en2x	huffman393
pre_dv	huffman393
pre_bits	huffman393
pre_len	huffman393
twe	huffman393
tdi	huffman393
ta	huffman393
clk	varlen_encode393	Input
en	varlen_encode393	Input
start	varlen_encode393	Input
d	varlen_encode393	Input
l	varlen_encode393	Output
l_late	varlen_encode393	Output
q	varlen_encode393	Output
d1	varlen_encode393	Signal
q0	varlen_encode393	Signal
cycles	varlen_encode393	Signal
this0	varlen_encode393	Signal
this1	varlen_encode393	Signal
this2	varlen_encode393	Signal
codel0	varlen_encode393	Signal
codel1	varlen_encode393	Signal
codel2	varlen_encode393	Signal
codel	varlen_encode393	Signal
ALWAYS_150 xclk	huff_fifo393	Always Construct
ALWAYS_151 xclk2x	huff_fifo393	Always Construct
ALWAYS_152 xclk2x	huff_fifo393	Always Construct
ALWAYS_153 xclk2x	huffman393	Always Construct
ALWAYS_154 xclk2x	huffman393	Always Construct
ALWAYS_155 xclk2x	huffman393	Always Construct
ALWAYS_156 xclk2x	huffman393	Always Construct
ALWAYS_157 xclk2x	huffman393	Always Construct
ALWAYS_158 xclk2x	huffman393	Always Construct
ALWAYS_159 xclk2x	huffman393	Always Construct
ALWAYS_160 xclk2x	huffman393	Always Construct
ALWAYS_161 xclk2x	huffman393	Always Construct
ALWAYS_162 xclk2x	huffman393	Always Construct
ALWAYS_192 clk	varlen_encode393	Always Construct
ALWAYS_193 clk	varlen_encode393	Always Construct
ALWAYS_194 clk	varlen_encode393	Always Construct
ALWAYS_195 clk	varlen_encode393	Always Construct
ALWAYS_532 src_clk or rst	pulse_cross_clock	Always Construct
ALWAYS_533 dst_clk	pulse_cross_clock	Always Construct
ALWAYS_549 clk	table_ad_receive	Always Construct
GENERATE [123]	ram18_var_w_var_r	GENERATE
GENERATE [54]	latch_g_ce	GENERATE
GENERATE [68]	table_ad_receive	GENERATE
huff_fifo393	huffman393
huffman.dat.vh	huffman393
latch_g_ce	huffman393
latch_g_ce	huffman393
latch_g_ce	huffman393
latch_g_ce	huffman393
latch_g_ce	huffman393
LDCE	latch_g_ce	Module Instance
pulse_cross_clock	huffman393
ram18_32w_32r	ram18_var_w_var_r	Module Instance
ram18_32w_lt32r	ram18_var_w_var_r	Module Instance
ram18_declare_init.vh	ram18_var_w_var_r	Include
ram18_dummy	ram18_var_w_var_r	Module Instance
ram18_lt32w_32r	ram18_var_w_var_r	Module Instance
ram18_lt32w_lt32r	ram18_var_w_var_r	Module Instance
ram18_pass_init.vh	ram18_var_w_var_r	Include
ram18_var_w_var_r	huffman393
ram18_var_w_var_r.RAMB18E1	ram18_32w_32r	Module Instance
ram18_var_w_var_r.ram18_32w_lt32r.RAMB18E1	ram18_32w_lt32r	Module Instance
ram18_var_w_var_r.ram18_lt32w_32r.RAMB18E1	ram18_lt32w_32r	Module Instance
ram18_var_w_var_r.ram18_lt32w_lt32r.RAMB18E1	ram18_lt32w_lt32r	Module Instance
table_ad_receive	huffman393
varlen_encode393	huffman393