axi_ahci_regs Member List

This is the complete list of members for axi_ahci_regs, including all inherited members.

ADDRESS_BITS	axibram_read	Parameter
write_left	axibram_write	Signal
wburst	axibram_write	Signal
wlen	axibram_write	Signal
DATA_WIDTH	fifo_cross_clocks	Parameter
DATA_DEPTH	fifo_cross_clocks	Parameter
rst	fifo_cross_clocks	Input
rrst	fifo_cross_clocks	Input
wrst	fifo_cross_clocks	Input
rclk	fifo_cross_clocks	Input
next_wr_address_w	axibram_write	Signal
wclk	fifo_cross_clocks	Input
we	fifo_cross_clocks	Input
re	fifo_cross_clocks	Input
data_in	fifo_cross_clocks	Input
data_out	fifo_cross_clocks	Output
nempty	fifo_cross_clocks	Output
half_empty	fifo_cross_clocks	Output
DATA_2DEPTH	fifo_cross_clocks	Parameter
ram	fifo_cross_clocks	Signal
raddr	fifo_cross_clocks	Signal
waddr	fifo_cross_clocks	Signal
waddr_gray	fifo_cross_clocks	Signal
waddr_gray_rclk	fifo_cross_clocks	Signal
waddr_plus1	fifo_cross_clocks	Signal
waddr_plus1_gray	fifo_cross_clocks	Signal
raddr_gray	fifo_cross_clocks	Signal
raddr_plus1	fifo_cross_clocks	Signal
raddr_plus1_gray_top3	fifo_cross_clocks	Signal
raddr_gray_top3	fifo_cross_clocks	Signal
raddr_gray_top3_wclk	fifo_cross_clocks	Signal
raddr_top3_wclk	fifo_cross_clocks	Signal
waddr_top3	fifo_cross_clocks	Signal
addr_diff	fifo_cross_clocks	Signal
DATA_WIDTH	fifo_same_clock	Parameter
DATA_DEPTH	fifo_same_clock	Parameter
rst	fifo_same_clock	Input
clk	fifo_same_clock	Input
sync_rst	fifo_same_clock	Input
we	fifo_same_clock	Input
re	fifo_same_clock	Input
data_in	fifo_same_clock	Input
data_out	fifo_same_clock	Output
nempty	fifo_same_clock	Output
half_full	fifo_same_clock	Output
DATA_2DEPTH	fifo_same_clock	Parameter
fill	fifo_same_clock	Signal
inreg	fifo_same_clock	Signal
outreg	fifo_same_clock	Signal
ra	fifo_same_clock	Signal
wa	fifo_same_clock	Signal
wem	fifo_same_clock	Signal
rem	fifo_same_clock	Signal
out_full	fifo_same_clock	Signal
ram	fifo_same_clock	Signal
ram_nempty	fifo_same_clock	Signal
bram_we_w	axibram_write	Signal
start_write_burst_w	axibram_write	Signal
write_in_progress_w	axibram_write	Signal
EXTRA_DLY	pulse_cross_clock	Parameter
rst	pulse_cross_clock	Input
src_clk	pulse_cross_clock	Input
dst_clk	pulse_cross_clock	Input
in_pulse	pulse_cross_clock	Input
out_pulse	pulse_cross_clock	Output
busy	pulse_cross_clock	Output
EXTRA_DLY_SAFE	pulse_cross_clock	Parameter
in_reg	pulse_cross_clock	Signal
out_reg	pulse_cross_clock	Signal
busy_r	pulse_cross_clock	Signal
aw_nempty_ready	axibram_write	Signal
w_nempty_ready	axibram_write	Signal
dev_ready_r	axibram_write	Signal
rdata	axibram_read	Output
bresp_in	axibram_write	Signal
was_bresp_re	axibram_write	Signal
bresp_re	axibram_write	Signal
REGISTERS	ram_var_w_var_r	Parameter
LOG2WIDTH_WR	ram_var_w_var_r	Parameter
LOG2WIDTH_RD	ram_var_w_var_r	Parameter
11862	ram_var_w_var_r	Parameter
rclk	ram_var_w_var_r	Input
raddr	ram_var_w_var_r	Input
ren	ram_var_w_var_r	Input
regen	ram_var_w_var_r	Input
data_out	ram_var_w_var_r	Output
wclk	ram_var_w_var_r	Input
waddr	ram_var_w_var_r	Input
we	ram_var_w_var_r	Input
web	ram_var_w_var_r	Input
data_in	ram_var_w_var_r	Input
rvalid	axibram_read	Output
REGISTERS_A	ramt_var_wb_var_r	Parameter
REGISTERS_B	ramt_var_wb_var_r	Parameter
LOG2WIDTH_A	ramt_var_wb_var_r	Parameter
LOG2WIDTH_B	ramt_var_wb_var_r	Parameter
WRITE_MODE_A	ramt_var_wb_var_r	Parameter
12068	ramt_var_wb_var_r	Parameter
clk_a	ramt_var_wb_var_r	Input
addr_a	ramt_var_wb_var_r	Input
en_a	ramt_var_wb_var_r	Input
regen_a	ramt_var_wb_var_r	Input
we_a	ramt_var_wb_var_r	Input
data_out_a	ramt_var_wb_var_r	Output
data_in_a	ramt_var_wb_var_r	Input
clk_b	ramt_var_wb_var_r	Input
addr_b	ramt_var_wb_var_r	Input
en_b	ramt_var_wb_var_r	Input
regen_b	ramt_var_wb_var_r	Input
we_b	ramt_var_wb_var_r	Input
data_out_b	ramt_var_wb_var_r	Output
data_in_b	ramt_var_wb_var_r	Input
PWIDTH_A	ramt_var_wb_var_r	Parameter
PWIDTH_B	ramt_var_wb_var_r	Parameter
WIDTH_A	ramt_var_wb_var_r	Parameter
WIDTH_B	ramt_var_wb_var_r	Parameter
data_out32_a	ramt_var_wb_var_r	Signal
data_out32_b	ramt_var_wb_var_r	Signal
data_in_ext_a	ramt_var_wb_var_r	Signal
data_in32_a	ramt_var_wb_var_r	Signal
data_in_ext_b	ramt_var_wb_var_r	Signal
data_in32_b	ramt_var_wb_var_r	Signal
we_a4	ramt_var_wb_var_r	Signal
we_b4	ramt_var_wb_var_r	Signal
rready	axibram_read	Input
rid	axibram_read	Output
ADDRESS_BITS	axi_ahci_regs
HBA_RESET_BITS	axi_ahci_regs
RESET_TO_FIRST_ACCESS	axi_ahci_regs
aclk	axi_ahci_regs
arst	axi_ahci_regs
awaddr	axi_ahci_regs
awvalid	axi_ahci_regs
awready	axi_ahci_regs
awid	axi_ahci_regs
awlen	axi_ahci_regs
awsize	axi_ahci_regs
awburst	axi_ahci_regs
wdata	axi_ahci_regs
wvalid	axi_ahci_regs
wready	axi_ahci_regs
wid	axi_ahci_regs
wlast	axi_ahci_regs
wstb	axi_ahci_regs
bvalid	axi_ahci_regs
bready	axi_ahci_regs
bid	axi_ahci_regs
bresp	axi_ahci_regs
araddr	axi_ahci_regs
arvalid	axi_ahci_regs
arready	axi_ahci_regs
arid	axi_ahci_regs
arlen	axi_ahci_regs
arsize	axi_ahci_regs
arburst	axi_ahci_regs
rdata	axi_ahci_regs
rvalid	axi_ahci_regs
rready	axi_ahci_regs
rid	axi_ahci_regs
rlast	axi_ahci_regs
rresp	axi_ahci_regs
soft_write_addr	axi_ahci_regs
soft_write_data	axi_ahci_regs
soft_write_en	axi_ahci_regs
hba_arst	axi_ahci_regs
port_arst	axi_ahci_regs
port_arst_any	axi_ahci_regs
hba_clk	axi_ahci_regs
hba_rst	axi_ahci_regs
hba_addr	axi_ahci_regs
hba_we	axi_ahci_regs
hba_re	axi_ahci_regs
hba_din	axi_ahci_regs
hba_dout	axi_ahci_regs
pgm_ad	axi_ahci_regs
pgm_wa	axi_ahci_regs
pgm_wd	axi_ahci_regs
afi_wcache	axi_ahci_regs
afi_rcache	axi_ahci_regs
afi_cache_set	axi_ahci_regs
was_hba_rst	axi_ahci_regs
was_port_rst	axi_ahci_regs
debug_in0	axi_ahci_regs
debug_in1	axi_ahci_regs
debug_in2	axi_ahci_regs
debug_in3	axi_ahci_regs
drp_en	axi_ahci_regs
drp_we	axi_ahci_regs
drp_addr	axi_ahci_regs
drp_di	axi_ahci_regs
drp_rdy	axi_ahci_regs
drp_do	axi_ahci_regs
datascope_clk	axi_ahci_regs
datascope_waddr	axi_ahci_regs
datascope_we	axi_ahci_regs
datascope_di	axi_ahci_regs
datascope1_clk	axi_ahci_regs
datascope1_waddr	axi_ahci_regs
datascope1_we	axi_ahci_regs
datascope1_di	axi_ahci_regs
DRP_ADDR	axi_ahci_regs
drp_read_data	axi_ahci_regs
drp_read_r	axi_ahci_regs
drp_ready_r	axi_ahci_regs
AXIBRAM_BITS	axi_ahci_regs
datascope_rdata	axi_ahci_regs
datascope_sel	axi_ahci_regs
datascope1_rdata	axi_ahci_regs
datascope1_sel	axi_ahci_regs
bram_waddr	axi_ahci_regs
bram_raddr	axi_ahci_regs
bram_rdata	axi_ahci_regs
pre_bram_wen	axi_ahci_regs
bram_wen	axi_ahci_regs
bram_wstb	axi_ahci_regs
bram_wdata	axi_ahci_regs
bram_addr	axi_ahci_regs
bram_ren	axi_ahci_regs
write_busy_r	axi_ahci_regs
write_start_burst	axi_ahci_regs
write_busy_w	axi_ahci_regs
bram_wdata_r	axi_ahci_regs
bram_rdata_r	axi_ahci_regs
regbit_type	axi_ahci_regs
ahci_regs_di	axi_ahci_regs
bram_wstb_r	axi_ahci_regs
bram_wen_r	axi_ahci_regs
wmask	axi_ahci_regs
bram_waddr_r	axi_ahci_regs
hba_reset_cntr	axi_ahci_regs
hba_rst_r	axi_ahci_regs
port_rst_r	axi_ahci_regs
port_arst_any_r	axi_ahci_regs
high_sel	axi_ahci_regs
afi_cache_set_w	axi_ahci_regs
pgm_fsm_set_w	axi_ahci_regs
pgm_fsm_and_w	axi_ahci_regs
set_hba_rst	axi_ahci_regs
HBA_PORT__PxSCTL__DET__MASK01	axi_ahci_regs
set_port_rst	axi_ahci_regs
port_rst_on	axi_ahci_regs
was_hba_rst_aclk	axi_ahci_regs
was_port_rst_aclk	axi_ahci_regs
was_hba_rst_r	axi_ahci_regs
was_port_rst_r	axi_ahci_regs
arst_r	axi_ahci_regs
wait_first_access	axi_ahci_regs
any_access	axi_ahci_regs
debug_rd_r	axi_ahci_regs
debug_r	axi_ahci_regs
rlast	axibram_read	Output
rresp	axibram_read	Output
pre_araddr	axibram_read	Output
start_burst	axibram_read	Output
dev_ready	axibram_read	Input
bram_rclk	axibram_read	Output
aclk	axibram_read	Input
bram_raddr	axibram_read	Output
bram_ren	axibram_read	Output
bram_regen	axibram_read	Output
bram_rdata	axibram_read	Input
ar_nempty	axibram_read	Signal
ar_half_full	axibram_read	Signal
arburst_out	axibram_read	Signal
arsize_out	axibram_read	Signal
arlen_out	axibram_read	Signal
araddr_out	axibram_read	Signal
arst	axibram_read	Input
arid_out	axibram_read	Signal
read_in_progress	axibram_read	Signal
read_in_progress_d	axibram_read	Signal
read_in_progress_or	axibram_read	Signal
read_address	axibram_read	Signal
read_left	axibram_read	Signal
rburst	axibram_read	Signal
rlen	axibram_read	Signal
next_rd_address_w	axibram_read	Signal
start_read_burst_w	axibram_read	Signal
araddr	axibram_read	Input
bram_reg_re_w	axibram_read	Signal
read_in_progress_w	axibram_read	Signal
read_in_progress_d_w	axibram_read	Signal
last_in_burst_w	axibram_read	Signal
last_in_burst_d_w	axibram_read	Signal
pre_last_in_burst_r	axibram_read	Signal
pre_rvalid_w	axibram_read	Signal
pre_left_zero_w	axibram_read	Signal
bram_reg_re_0	axibram_read	Signal
last_in_burst_1	axibram_read	Signal
arvalid	axibram_read	Input
last_in_burst_0	axibram_read	Signal
start_read_burst_0	axibram_read	Signal
start_read_burst_1	axibram_read	Signal
pre_rid0	axibram_read	Signal
pre_rid	axibram_read	Signal
bram_regen_r	axibram_read	Signal
ADDRESS_BITS	axibram_write	Parameter
aclk	axibram_write	Input
arst	axibram_write	Input
awaddr	axibram_write	Input
arready	axibram_read	Output
awvalid	axibram_write	Input
awready	axibram_write	Output
awid	axibram_write	Input
awlen	axibram_write	Input
awsize	axibram_write	Input
awburst	axibram_write	Input
wdata	axibram_write	Input
wvalid	axibram_write	Input
wready	axibram_write	Output
wid	axibram_write	Input
arid	axibram_read	Input
wlast	axibram_write	Input
wstb	axibram_write	Input
bvalid	axibram_write	Output
bready	axibram_write	Input
bid	axibram_write	Output
bresp	axibram_write	Output
pre_awaddr	axibram_write	Output
start_burst	axibram_write	Output
dev_ready	axibram_write	Input
bram_wclk	axibram_write	Output
arlen	axibram_read	Input
bram_waddr	axibram_write	Output
pre_bram_wen	axibram_write	Output
bram_wen	axibram_write	Output
bram_wstb	axibram_write	Output
bram_wdata	axibram_write	Output
aw_nempty	axibram_write	Signal
aw_half_full	axibram_write	Signal
awburst_out	axibram_write	Signal
awsize_out	axibram_write	Signal
awlen_out	axibram_write	Signal
arsize	axibram_read	Input
awaddr_out	axibram_write	Signal
awid_out	axibram_write	Signal
w_nempty	axibram_write	Signal
w_half_full	axibram_write	Signal
wdata_out	axibram_write	Signal
wlast_out	axibram_write	Signal
wstb_out	axibram_write	Signal
wid_out	axibram_write	Signal
write_in_progress	axibram_write	Signal
write_address	axibram_write	Signal
arburst	axibram_read	Input
ahci_defaults.vh	axi_ahci_regs
ahci_localparams.vh	axi_ahci_regs
ahci_types.vh	axi_ahci_regs
ALWAYS_0 aclk	axibram_read	Always Construct
ALWAYS_1 aclk	axibram_read	Always Construct
ALWAYS_2 aclk	axibram_write	Always Construct
ALWAYS_3 aclk	axibram_write	Always Construct
ALWAYS_504 wclk or rst	fifo_cross_clocks	Always Construct
ALWAYS_505 rclk or rst	fifo_cross_clocks	Always Construct
ALWAYS_506 rclk	fifo_cross_clocks	Always Construct
ALWAYS_507 wclk	fifo_cross_clocks	Always Construct
ALWAYS_508 clk or rst	fifo_same_clock	Always Construct
ALWAYS_509 clk	fifo_same_clock	Always Construct
ALWAYS_532 src_clk or rst	pulse_cross_clock	Always Construct
ALWAYS_533 dst_clk	pulse_cross_clock	Always Construct
ALWAYS_594 aclk	axi_ahci_regs	Always Construct
ALWAYS_595 aclk	axi_ahci_regs	Always Construct
ALWAYS_596 aclk	axi_ahci_regs	Always Construct
ALWAYS_597 aclk	axi_ahci_regs	Always Construct
ALWAYS_598 hba_clk	axi_ahci_regs	Always Construct
ALWAYS_599 aclk	axi_ahci_regs	Always Construct
ALWAYS_600 aclk	axi_ahci_regs	Always Construct
axibram_read	axi_ahci_regs
axibram_write	axi_ahci_regs
fifo_cross_clocks	axi_ahci_regs
axibram_write.fifo_same_clock	axibram_write	Module Instance
axibram_write.fifo_same_clock	axibram_write	Module Instance
axibram_write.fifo_same_clock	axibram_write	Module Instance
axibram_read.fifo_same_clock	axibram_read	Module Instance
GENERATE [107]	ram_var_w_var_r	GENERATE
GENERATE [284]	axi_ahci_regs
pulse_cross_clock	axi_ahci_regs
ramt_var_wb_var_r.ram36_declare_init.vh	ramt_var_wb_var_r	Include
ram_var_w_var_r.ram36_declare_init.vh	ram_var_w_var_r	Include
ramt_var_wb_var_r.ram36_pass_init.vh	ramt_var_wb_var_r	Include
ram_var_w_var_r.ram36_pass_init.vh	ram_var_w_var_r	Include
ram_64w_64r	ram_var_w_var_r	Module Instance
ram_64w_lt64r	ram_var_w_var_r	Module Instance
ram_dummy	ram_var_w_var_r	Module Instance
ram_lt64w_64r	ram_var_w_var_r	Module Instance
ram_lt64w_lt64r	ram_var_w_var_r	Module Instance
ram_var_w_var_r	axi_ahci_regs
ram_var_w_var_r	axi_ahci_regs
ram_var_w_var_r	axi_ahci_regs
ramt_var_wb_var_r.RAMB36E1	ramt_var_wb_var_r	Module Instance
ram_var_w_var_r.ram_64w_64r.RAMB36E1	ram_64w_64r	Module Instance
ram_var_w_var_r.ram_64w_lt64r.RAMB36E1	ram_64w_lt64r	Module Instance
ram_var_w_var_r.ram_lt64w_64r.RAMB36E1	ram_lt64w_64r	Module Instance
ram_var_w_var_r.ram_lt64w_lt64r.RAMB36E1	ram_lt64w_lt64r	Module Instance
ramt_var_wb_var_r	axi_ahci_regs