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00034 #include <linux/module.h>
00035 #include <linux/delay.h>
00036 #include <linux/errno.h>
00037 #include <linux/err.h>
00038 #include <linux/sched.h>
00039 #include <linux/slab.h>
00040 #include <linux/types.h>
00041 #include <linux/mtd/mtd.h>
00042 #include <linux/mtd/nand.h>
00043 #include <linux/mtd/nand_ecc.h>
00044 #include <linux/mtd/compatmac.h>
00045 #include <linux/interrupt.h>
00046 #include <linux/bitops.h>
00047 #include <linux/leds.h>
00048 #include <asm/io.h>
00049
00050 #ifdef CONFIG_MTD_PARTITIONS
00051 #include <linux/mtd/partitions.h>
00052 #endif
00053
00054
00055 static struct nand_ecclayout nand_oob_8 = {
00056 .eccbytes = 3,
00057 .eccpos = {0, 1, 2},
00058 .oobfree = {
00059 {.offset = 3,
00060 .length = 2},
00061 {.offset = 6,
00062 .length = 2}}
00063 };
00064
00065 static struct nand_ecclayout nand_oob_16 = {
00066 .eccbytes = 6,
00067 .eccpos = {0, 1, 2, 3, 6, 7},
00068 .oobfree = {
00069 {.offset = 8,
00070 . length = 8}}
00071 };
00072
00073 static struct nand_ecclayout nand_oob_64 = {
00074 .eccbytes = 24,
00075 .eccpos = {
00076 40, 41, 42, 43, 44, 45, 46, 47,
00077 48, 49, 50, 51, 52, 53, 54, 55,
00078 56, 57, 58, 59, 60, 61, 62, 63},
00079 .oobfree = {
00080 {.offset = 2,
00081 .length = 38}}
00082 };
00083
00084 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
00085 int new_state);
00086
00087 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
00088 struct mtd_oob_ops *ops);
00089
00090
00091
00092
00093
00094 DEFINE_LED_TRIGGER(nand_led_trigger);
00095
00102 static void nand_release_device(struct mtd_info *mtd)
00103 {
00104 struct nand_chip *chip = mtd->priv;
00105
00106
00107 chip->select_chip(mtd, -1);
00108
00109
00110 spin_lock(&chip->controller->lock);
00111 chip->controller->active = NULL;
00112 chip->state = FL_READY;
00113 wake_up(&chip->controller->wq);
00114 spin_unlock(&chip->controller->lock);
00115 }
00116
00123 static uint8_t nand_read_byte(struct mtd_info *mtd)
00124 {
00125 struct nand_chip *chip = mtd->priv;
00126 return readb(chip->IO_ADDR_R);
00127 }
00128
00136 static uint8_t nand_read_byte16(struct mtd_info *mtd)
00137 {
00138 struct nand_chip *chip = mtd->priv;
00139 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
00140 }
00141
00149 static u16 nand_read_word(struct mtd_info *mtd)
00150 {
00151 struct nand_chip *chip = mtd->priv;
00152 return readw(chip->IO_ADDR_R);
00153 }
00154
00162 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
00163 {
00164 struct nand_chip *chip = mtd->priv;
00165
00166 switch (chipnr) {
00167 case -1:
00168 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
00169 break;
00170 case 0:
00171 break;
00172
00173 default:
00174 BUG();
00175 }
00176 }
00177
00186 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
00187 {
00188 int i;
00189 struct nand_chip *chip = mtd->priv;
00190
00191 for (i = 0; i < len; i++)
00192 writeb(buf[i], chip->IO_ADDR_W);
00193 }
00194
00203 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
00204 {
00205 int i;
00206 struct nand_chip *chip = mtd->priv;
00207
00208 for (i = 0; i < len; i++)
00209 buf[i] = readb(chip->IO_ADDR_R);
00210 if (!(chip->dev_ready(mtd))) printk("==================================Lost READY while reading buffer!\n");
00211
00212 }
00213
00222 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
00223 {
00224 int i;
00225 struct nand_chip *chip = mtd->priv;
00226
00227
00228 for (i = 0; i < len; i++)
00229 if (buf[i] != readb(chip->IO_ADDR_R))
00230 return -EFAULT;
00231 return 0;
00232 }
00233
00242 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
00243 {
00244 int i;
00245 struct nand_chip *chip = mtd->priv;
00246 u16 *p = (u16 *) buf;
00247 len >>= 1;
00248
00249 for (i = 0; i < len; i++)
00250 writew(p[i], chip->IO_ADDR_W);
00251
00252 }
00253
00262 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
00263 {
00264 int i;
00265 struct nand_chip *chip = mtd->priv;
00266 u16 *p = (u16 *) buf;
00267 len >>= 1;
00268
00269 for (i = 0; i < len; i++)
00270 p[i] = readw(chip->IO_ADDR_R);
00271 }
00272
00281 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
00282 {
00283 int i;
00284 struct nand_chip *chip = mtd->priv;
00285 u16 *p = (u16 *) buf;
00286 len >>= 1;
00287
00288 for (i = 0; i < len; i++)
00289 if (p[i] != readw(chip->IO_ADDR_R))
00290 return -EFAULT;
00291
00292 return 0;
00293 }
00294
00303 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
00304 {
00305 int page, chipnr, res = 0;
00306 struct nand_chip *chip = mtd->priv;
00307 u16 bad;
00308
00309 if (getchip) {
00310 page = (int)(ofs >> chip->page_shift);
00311 chipnr = (int)(ofs >> chip->chip_shift);
00312
00313 nand_get_device(chip, mtd, FL_READING);
00314
00315
00316 chip->select_chip(mtd, chipnr);
00317 } else
00318 page = (int)ofs;
00319
00320 if (chip->options & NAND_BUSWIDTH_16) {
00321 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
00322 page & chip->pagemask);
00323 bad = cpu_to_le16(chip->read_word(mtd));
00324 if (chip->badblockpos & 0x1)
00325 bad >>= 8;
00326 if ((bad & 0xFF) != 0xff)
00327 res = 1;
00328 } else {
00329 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
00330 page & chip->pagemask);
00331 if (chip->read_byte(mtd) != 0xff)
00332 res = 1;
00333 }
00334
00335 if (getchip)
00336 nand_release_device(mtd);
00337
00338 return res;
00339 }
00340
00349 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
00350 {
00351 struct nand_chip *chip = mtd->priv;
00352 uint8_t buf[2] = { 0, 0 };
00353 int block, ret;
00354
00355
00356 block = ((int)ofs) >> chip->bbt_erase_shift;
00357 if (chip->bbt)
00358 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
00359
00360
00361 if (chip->options & NAND_USE_FLASH_BBT)
00362 ret = nand_update_bbt(mtd, ofs);
00363 else {
00364
00365
00366
00367 ofs += mtd->oobsize;
00368 chip->ops.len = chip->ops.ooblen = 2;
00369 chip->ops.datbuf = NULL;
00370 chip->ops.oobbuf = buf;
00371 chip->ops.ooboffs = chip->badblockpos & ~0x01;
00372
00373 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
00374 }
00375 if (!ret)
00376 mtd->ecc_stats.badblocks++;
00377 return ret;
00378 }
00379
00387 static int nand_check_wp(struct mtd_info *mtd)
00388 {
00389 struct nand_chip *chip = mtd->priv;
00390
00391 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
00392 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
00393 }
00394
00405 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
00406 int allowbbt)
00407 {
00408 struct nand_chip *chip = mtd->priv;
00409
00410 if (!chip->bbt)
00411 return chip->block_bad(mtd, ofs, getchip);
00412
00413
00414 return nand_isbad_bbt(mtd, ofs, allowbbt);
00415 }
00416
00417
00418
00419
00420
00421 void nand_wait_ready(struct mtd_info *mtd)
00422 {
00423 struct nand_chip *chip = mtd->priv;
00424 unsigned long timeo = jiffies + 2;
00425
00426 led_trigger_event(nand_led_trigger, LED_FULL);
00427
00428 do {
00429 if (chip->dev_ready(mtd))
00430 break;
00431 touch_softlockup_watchdog();
00432 } while (time_before(jiffies, timeo));
00433 led_trigger_event(nand_led_trigger, LED_OFF);
00434 }
00435 EXPORT_SYMBOL_GPL(nand_wait_ready);
00436
00447 static void nand_command(struct mtd_info *mtd, unsigned int command,
00448 int column, int page_addr)
00449 {
00450 register struct nand_chip *chip = mtd->priv;
00451 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
00452
00453
00454
00455
00456 if (command == NAND_CMD_SEQIN) {
00457 int readcmd;
00458
00459 if (column >= mtd->writesize) {
00460
00461 column -= mtd->writesize;
00462 readcmd = NAND_CMD_READOOB;
00463 } else if (column < 256) {
00464
00465 readcmd = NAND_CMD_READ0;
00466 } else {
00467 column -= 256;
00468 readcmd = NAND_CMD_READ1;
00469 }
00470 chip->cmd_ctrl(mtd, readcmd, ctrl);
00471 ctrl &= ~NAND_CTRL_CHANGE;
00472 }
00473 chip->cmd_ctrl(mtd, command, ctrl);
00474
00475
00476
00477
00478 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
00479
00480 if (column != -1) {
00481
00482 if (chip->options & NAND_BUSWIDTH_16)
00483 column >>= 1;
00484 chip->cmd_ctrl(mtd, column, ctrl);
00485 ctrl &= ~NAND_CTRL_CHANGE;
00486 }
00487 if (page_addr != -1) {
00488 chip->cmd_ctrl(mtd, page_addr, ctrl);
00489 ctrl &= ~NAND_CTRL_CHANGE;
00490 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
00491
00492 if (chip->chipsize > (32 << 20))
00493 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
00494 }
00495 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
00496
00497
00498
00499
00500
00501 switch (command) {
00502
00503 case NAND_CMD_PAGEPROG:
00504 case NAND_CMD_ERASE1:
00505 case NAND_CMD_ERASE2:
00506 case NAND_CMD_SEQIN:
00507 case NAND_CMD_STATUS:
00508 return;
00509
00510 case NAND_CMD_RESET:
00511 if (chip->dev_ready)
00512 break;
00513 udelay(chip->chip_delay);
00514 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
00515 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
00516 chip->cmd_ctrl(mtd,
00517 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
00518 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
00519 return;
00520
00521
00522 default:
00523
00524
00525
00526
00527 if (!chip->dev_ready) {
00528 udelay(chip->chip_delay);
00529 return;
00530 }
00531 }
00532
00533
00534 ndelay(100);
00535
00536 nand_wait_ready(mtd);
00537 }
00538
00550 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
00551 int column, int page_addr)
00552 {
00553 register struct nand_chip *chip = mtd->priv;
00554
00555
00556 if (command == NAND_CMD_READOOB) {
00557 column += mtd->writesize;
00558 command = NAND_CMD_READ0;
00559 }
00560
00561
00562
00563
00564 chip->cmd_ctrl(mtd, command & 0xff,
00565 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
00566
00567 if (column != -1 || page_addr != -1) {
00568 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
00569
00570
00571 if (column != -1) {
00572
00573 if (chip->options & NAND_BUSWIDTH_16)
00574 column >>= 1;
00575 chip->cmd_ctrl(mtd, column, ctrl);
00576 ctrl &= ~NAND_CTRL_CHANGE;
00577 chip->cmd_ctrl(mtd, column >> 8, ctrl);
00578 }
00579 if (page_addr != -1) {
00580 chip->cmd_ctrl(mtd, page_addr, ctrl);
00581 chip->cmd_ctrl(mtd, page_addr >> 8,
00582 NAND_NCE | NAND_ALE);
00583
00584 if (chip->chipsize > (128 << 20))
00585 chip->cmd_ctrl(mtd, page_addr >> 16,
00586 NAND_NCE | NAND_ALE);
00587 }
00588 }
00589 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
00590
00591
00592
00593
00594 switch (command) {
00595
00596 case NAND_CMD_CACHEDPROG:
00597 case NAND_CMD_PAGEPROG:
00598 case NAND_CMD_ERASE1:
00599 case NAND_CMD_ERASE2:
00600 case NAND_CMD_SEQIN:
00601 case NAND_CMD_RNDIN:
00602 case NAND_CMD_STATUS:
00603 case NAND_CMD_DEPLETE1:
00604 return;
00605
00606
00607
00608
00609 case NAND_CMD_STATUS_ERROR:
00610 case NAND_CMD_STATUS_ERROR0:
00611 case NAND_CMD_STATUS_ERROR1:
00612 case NAND_CMD_STATUS_ERROR2:
00613 case NAND_CMD_STATUS_ERROR3:
00614 udelay(chip->chip_delay);
00615 return;
00616
00617 case NAND_CMD_RESET:
00618 if (chip->dev_ready)
00619 break;
00620 udelay(chip->chip_delay);
00621 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
00622 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
00623 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
00624 NAND_NCE | NAND_CTRL_CHANGE);
00625 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
00626 return;
00627
00628 case NAND_CMD_RNDOUT:
00629
00630 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
00631 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
00632 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
00633 NAND_NCE | NAND_CTRL_CHANGE);
00634 return;
00635
00636 case NAND_CMD_READ0:
00637 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
00638 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
00639 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
00640 NAND_NCE | NAND_CTRL_CHANGE);
00641
00642
00643 default:
00644
00645
00646
00647
00648 if (!chip->dev_ready) {
00649 udelay(chip->chip_delay);
00650 return;
00651 }
00652 }
00653
00654
00655
00656 ndelay(100);
00657
00658 nand_wait_ready(mtd);
00659 }
00660
00669 static int
00670 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
00671 {
00672 spinlock_t *lock = &chip->controller->lock;
00673 wait_queue_head_t *wq = &chip->controller->wq;
00674 DECLARE_WAITQUEUE(wait, current);
00675 retry:
00676 spin_lock(lock);
00677
00678
00679
00680 if (!chip->controller->active)
00681 chip->controller->active = chip;
00682
00683 if (chip->controller->active == chip && chip->state == FL_READY) {
00684 chip->state = new_state;
00685 spin_unlock(lock);
00686 return 0;
00687 }
00688 if (new_state == FL_PM_SUSPENDED) {
00689 spin_unlock(lock);
00690 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
00691 }
00692 set_current_state(TASK_UNINTERRUPTIBLE);
00693 add_wait_queue(wq, &wait);
00694 spin_unlock(lock);
00695 schedule();
00696 remove_wait_queue(wq, &wait);
00697 goto retry;
00698 }
00699
00709 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
00710 {
00711
00712 unsigned long timeo = jiffies;
00713 int status, state = chip->state;
00714
00715 if (state == FL_ERASING)
00716 timeo += (HZ * 400) / 1000;
00717 else
00718 timeo += (HZ * 20) / 1000;
00719
00720 led_trigger_event(nand_led_trigger, LED_FULL);
00721
00722
00723
00724 ndelay(100);
00725
00726 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
00727 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
00728 else
00729 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
00730
00731 while (time_before(jiffies, timeo)) {
00732 if (chip->dev_ready) {
00733 if (chip->dev_ready(mtd))
00734 break;
00735 } else {
00736 if (chip->read_byte(mtd) & NAND_STATUS_READY)
00737 break;
00738 }
00739 cond_resched();
00740 }
00741 led_trigger_event(nand_led_trigger, LED_OFF);
00742
00743 status = (int)chip->read_byte(mtd);
00744 return status;
00745 }
00746
00753 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
00754 uint8_t *buf)
00755 {
00756 chip->read_buf(mtd, buf, mtd->writesize);
00757 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
00758 return 0;
00759 }
00760
00767 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
00768 uint8_t *buf)
00769 {
00770 int i, eccsize = chip->ecc.size;
00771 int eccbytes = chip->ecc.bytes;
00772 int eccsteps = chip->ecc.steps;
00773 uint8_t *p = buf;
00774 uint8_t *ecc_calc = chip->buffers->ecccalc;
00775 uint8_t *ecc_code = chip->buffers->ecccode;
00776 int *eccpos = chip->ecc.layout->eccpos;
00777
00778 nand_read_page_raw(mtd, chip, buf);
00779
00780 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
00781 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
00782
00783 for (i = 0; i < chip->ecc.total; i++)
00784 ecc_code[i] = chip->oob_poi[eccpos[i]];
00785
00786 eccsteps = chip->ecc.steps;
00787 p = buf;
00788
00789 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
00790 int stat;
00791
00792 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
00793 if (stat == -1)
00794 mtd->ecc_stats.failed++;
00795 else
00796 mtd->ecc_stats.corrected += stat;
00797 }
00798 return 0;
00799 }
00800
00809 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
00810 uint8_t *buf)
00811 {
00812 int i, eccsize = chip->ecc.size;
00813 int eccbytes = chip->ecc.bytes;
00814 int eccsteps = chip->ecc.steps;
00815 uint8_t *p = buf;
00816 uint8_t *ecc_calc = chip->buffers->ecccalc;
00817 uint8_t *ecc_code = chip->buffers->ecccode;
00818 int *eccpos = chip->ecc.layout->eccpos;
00819
00820 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
00821 chip->ecc.hwctl(mtd, NAND_ECC_READ);
00822 chip->read_buf(mtd, p, eccsize);
00823 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
00824 }
00825 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
00826
00827 for (i = 0; i < chip->ecc.total; i++)
00828 ecc_code[i] = chip->oob_poi[eccpos[i]];
00829
00830 eccsteps = chip->ecc.steps;
00831 p = buf;
00832
00833 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
00834 int stat;
00835
00836 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
00837 if (stat == -1)
00838 mtd->ecc_stats.failed++;
00839 else
00840 mtd->ecc_stats.corrected += stat;
00841 }
00842 return 0;
00843 }
00844
00854 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
00855 uint8_t *buf)
00856 {
00857 int i, eccsize = chip->ecc.size;
00858 int eccbytes = chip->ecc.bytes;
00859 int eccsteps = chip->ecc.steps;
00860 uint8_t *p = buf;
00861 uint8_t *oob = chip->oob_poi;
00862
00863 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
00864 int stat;
00865
00866 chip->ecc.hwctl(mtd, NAND_ECC_READ);
00867 chip->read_buf(mtd, p, eccsize);
00868
00869 if (chip->ecc.prepad) {
00870 chip->read_buf(mtd, oob, chip->ecc.prepad);
00871 oob += chip->ecc.prepad;
00872 }
00873
00874 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
00875 chip->read_buf(mtd, oob, eccbytes);
00876 stat = chip->ecc.correct(mtd, p, oob, NULL);
00877
00878 if (stat == -1)
00879 mtd->ecc_stats.failed++;
00880 else
00881 mtd->ecc_stats.corrected += stat;
00882
00883 oob += eccbytes;
00884
00885 if (chip->ecc.postpad) {
00886 chip->read_buf(mtd, oob, chip->ecc.postpad);
00887 oob += chip->ecc.postpad;
00888 }
00889 }
00890
00891
00892 i = mtd->oobsize - (oob - chip->oob_poi);
00893 if (i)
00894 chip->read_buf(mtd, oob, i);
00895
00896 return 0;
00897 }
00898
00905 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
00906 struct mtd_oob_ops *ops)
00907 {
00908 size_t len = ops->ooblen;
00909
00910 switch(ops->mode) {
00911
00912 case MTD_OOB_PLACE:
00913 case MTD_OOB_RAW:
00914 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
00915 return oob + len;
00916
00917 case MTD_OOB_AUTO: {
00918 struct nand_oobfree *free = chip->ecc.layout->oobfree;
00919 uint32_t boffs = 0, roffs = ops->ooboffs;
00920 size_t bytes = 0;
00921
00922 for(; free->length && len; free++, len -= bytes) {
00923
00924 if (unlikely(roffs)) {
00925 if (roffs >= free->length) {
00926 roffs -= free->length;
00927 continue;
00928 }
00929 boffs = free->offset + roffs;
00930 bytes = min_t(size_t, len,
00931 (free->length - roffs));
00932 roffs = 0;
00933 } else {
00934 bytes = min_t(size_t, len, free->length);
00935 boffs = free->offset;
00936 }
00937 memcpy(oob, chip->oob_poi + boffs, bytes);
00938 oob += bytes;
00939 }
00940 return oob;
00941 }
00942 default:
00943 BUG();
00944 }
00945 return NULL;
00946 }
00947
00957 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
00958 struct mtd_oob_ops *ops)
00959 {
00960 int chipnr, page, realpage, col, bytes, aligned;
00961 struct nand_chip *chip = mtd->priv;
00962 struct mtd_ecc_stats stats;
00963 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
00964 int sndcmd = 1;
00965 int ret = 0;
00966 uint32_t readlen = ops->len;
00967 uint8_t *bufpoi, *oob, *buf;
00968
00969 stats = mtd->ecc_stats;
00970
00971 chipnr = (int)(from >> chip->chip_shift);
00972 chip->select_chip(mtd, chipnr);
00973
00974 realpage = (int)(from >> chip->page_shift);
00975 page = realpage & chip->pagemask;
00976
00977 col = (int)(from & (mtd->writesize - 1));
00978 chip->oob_poi = chip->buffers->oobrbuf;
00979
00980 buf = ops->datbuf;
00981 oob = ops->oobbuf;
00982
00983 while(1) {
00984 bytes = min(mtd->writesize - col, readlen);
00985 aligned = (bytes == mtd->writesize);
00986
00987
00988 if (realpage != chip->pagebuf || oob) {
00989 bufpoi = aligned ? buf : chip->buffers->databuf;
00990
00991 if (likely(sndcmd)) {
00992 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
00993 sndcmd = 0;
00994 }
00995
00996
00997 if (unlikely(ops->mode == MTD_OOB_RAW))
00998 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi);
00999 else
01000 ret = chip->ecc.read_page(mtd, chip, bufpoi);
01001 if (ret < 0)
01002 break;
01003
01004
01005 if (!aligned) {
01006 chip->pagebuf = realpage;
01007 memcpy(buf, chip->buffers->databuf + col, bytes);
01008 }
01009
01010 buf += bytes;
01011
01012 if (unlikely(oob)) {
01013
01014 if (ops->mode != MTD_OOB_RAW)
01015 oob = nand_transfer_oob(chip, oob, ops);
01016 else
01017 buf = nand_transfer_oob(chip, buf, ops);
01018 }
01019
01020 if (!(chip->options & NAND_NO_READRDY)) {
01021
01022
01023
01024
01025
01026
01027
01028 if (!chip->dev_ready)
01029 udelay(chip->chip_delay);
01030 else
01031 nand_wait_ready(mtd);
01032 }
01033 } else {
01034 memcpy(buf, chip->buffers->databuf + col, bytes);
01035 buf += bytes;
01036 }
01037
01038 readlen -= bytes;
01039
01040 if (!readlen)
01041 break;
01042
01043
01044 col = 0;
01045
01046 realpage++;
01047
01048 page = realpage & chip->pagemask;
01049
01050 if (!page) {
01051 chipnr++;
01052 chip->select_chip(mtd, -1);
01053 chip->select_chip(mtd, chipnr);
01054 }
01055
01056
01057
01058
01059 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
01060 sndcmd = 1;
01061 }
01062
01063 ops->retlen = ops->len - (size_t) readlen;
01064
01065 if (ret)
01066 return ret;
01067
01068 if (mtd->ecc_stats.failed - stats.failed)
01069 return -EBADMSG;
01070
01071 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
01072 }
01073
01084 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
01085 size_t *retlen, uint8_t *buf)
01086 {
01087 struct nand_chip *chip = mtd->priv;
01088 int ret;
01089
01090
01091 if ((from + len) > mtd->size)
01092 return -EINVAL;
01093 if (!len)
01094 return 0;
01095
01096 nand_get_device(chip, mtd, FL_READING);
01097
01098 chip->ops.len = len;
01099 chip->ops.datbuf = buf;
01100 chip->ops.oobbuf = NULL;
01101
01102 ret = nand_do_read_ops(mtd, from, &chip->ops);
01103
01104 *retlen = chip->ops.retlen;
01105
01106 nand_release_device(mtd);
01107
01108 return ret;
01109 }
01110
01118 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
01119 int page, int sndcmd)
01120 {
01121 if (sndcmd) {
01122 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
01123 sndcmd = 0;
01124 }
01125 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
01126 return sndcmd;
01127 }
01128
01137 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
01138 int page, int sndcmd)
01139 {
01140 uint8_t *buf = chip->oob_poi;
01141 int length = mtd->oobsize;
01142 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
01143 int eccsize = chip->ecc.size;
01144 uint8_t *bufpoi = buf;
01145 int i, toread, sndrnd = 0, pos;
01146
01147 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
01148 for (i = 0; i < chip->ecc.steps; i++) {
01149 if (sndrnd) {
01150 pos = eccsize + i * (eccsize + chunk);
01151 if (mtd->writesize > 512)
01152 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
01153 else
01154 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
01155 } else
01156 sndrnd = 1;
01157 toread = min_t(int, length, chunk);
01158 chip->read_buf(mtd, bufpoi, toread);
01159 bufpoi += toread;
01160 length -= toread;
01161 }
01162 if (length > 0)
01163 chip->read_buf(mtd, bufpoi, length);
01164
01165 return 1;
01166 }
01167
01174 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
01175 int page)
01176 {
01177 int status = 0;
01178 const uint8_t *buf = chip->oob_poi;
01179 int length = mtd->oobsize;
01180
01181 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
01182 chip->write_buf(mtd, buf, length);
01183
01184 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
01185
01186 status = chip->waitfunc(mtd, chip);
01187
01188 return status & NAND_STATUS_FAIL ? -EIO : 0;
01189 }
01190
01198 static int nand_write_oob_syndrome(struct mtd_info *mtd,
01199 struct nand_chip *chip, int page)
01200 {
01201 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
01202 int eccsize = chip->ecc.size, length = mtd->oobsize;
01203 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
01204 const uint8_t *bufpoi = chip->oob_poi;
01205
01206
01207
01208
01209
01210
01211 if (!chip->ecc.prepad && !chip->ecc.postpad) {
01212 pos = steps * (eccsize + chunk);
01213 steps = 0;
01214 } else
01215 pos = eccsize;
01216
01217 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
01218 for (i = 0; i < steps; i++) {
01219 if (sndcmd) {
01220 if (mtd->writesize <= 512) {
01221 uint32_t fill = 0xFFFFFFFF;
01222
01223 len = eccsize;
01224 while (len > 0) {
01225 int num = min_t(int, len, 4);
01226 chip->write_buf(mtd, (uint8_t *)&fill,
01227 num);
01228 len -= num;
01229 }
01230 } else {
01231 pos = eccsize + i * (eccsize + chunk);
01232 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
01233 }
01234 } else
01235 sndcmd = 1;
01236 len = min_t(int, length, chunk);
01237 chip->write_buf(mtd, bufpoi, len);
01238 bufpoi += len;
01239 length -= len;
01240 }
01241 if (length > 0)
01242 chip->write_buf(mtd, bufpoi, length);
01243
01244 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
01245 status = chip->waitfunc(mtd, chip);
01246
01247 return status & NAND_STATUS_FAIL ? -EIO : 0;
01248 }
01249
01258 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
01259 struct mtd_oob_ops *ops)
01260 {
01261 int page, realpage, chipnr, sndcmd = 1;
01262 struct nand_chip *chip = mtd->priv;
01263 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
01264 int readlen = ops->len;
01265 uint8_t *buf = ops->oobbuf;
01266
01267 DEBUG(MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
01268 (unsigned long long)from, readlen);
01269
01270 chipnr = (int)(from >> chip->chip_shift);
01271 chip->select_chip(mtd, chipnr);
01272
01273
01274 realpage = (int)(from >> chip->page_shift);
01275 page = realpage & chip->pagemask;
01276
01277 chip->oob_poi = chip->buffers->oobrbuf;
01278
01279 while(1) {
01280 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
01281 buf = nand_transfer_oob(chip, buf, ops);
01282
01283 if (!(chip->options & NAND_NO_READRDY)) {
01284
01285
01286
01287
01288
01289
01290 if (!chip->dev_ready)
01291 udelay(chip->chip_delay);
01292 else
01293 nand_wait_ready(mtd);
01294 }
01295
01296 readlen -= ops->ooblen;
01297 if (!readlen)
01298 break;
01299
01300
01301 realpage++;
01302
01303 page = realpage & chip->pagemask;
01304
01305 if (!page) {
01306 chipnr++;
01307 chip->select_chip(mtd, -1);
01308 chip->select_chip(mtd, chipnr);
01309 }
01310
01311
01312
01313
01314 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
01315 sndcmd = 1;
01316 }
01317
01318 ops->retlen = ops->len;
01319 return 0;
01320 }
01321
01330 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
01331 struct mtd_oob_ops *ops)
01332 {
01333 struct nand_chip *chip = mtd->priv;
01334 int ret = -ENOTSUPP;
01335
01336 ops->retlen = 0;
01337
01338
01339 if ((from + ops->len) > mtd->size) {
01340 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
01341 "Attempt read beyond end of device\n");
01342 return -EINVAL;
01343 }
01344
01345 nand_get_device(chip, mtd, FL_READING);
01346
01347 switch(ops->mode) {
01348 case MTD_OOB_PLACE:
01349 case MTD_OOB_AUTO:
01350 case MTD_OOB_RAW:
01351 break;
01352
01353 default:
01354 goto out;
01355 }
01356
01357 if (!ops->datbuf)
01358 ret = nand_do_read_oob(mtd, from, ops);
01359 else
01360 ret = nand_do_read_ops(mtd, from, ops);
01361
01362 out:
01363 nand_release_device(mtd);
01364 return ret;
01365 }
01366
01367
01374 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
01375 const uint8_t *buf)
01376 {
01377 chip->write_buf(mtd, buf, mtd->writesize);
01378 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
01379 }
01380
01387 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
01388 const uint8_t *buf)
01389 {
01390 int i, eccsize = chip->ecc.size;
01391 int eccbytes = chip->ecc.bytes;
01392 int eccsteps = chip->ecc.steps;
01393 uint8_t *ecc_calc = chip->buffers->ecccalc;
01394 const uint8_t *p = buf;
01395 int *eccpos = chip->ecc.layout->eccpos;
01396
01397
01398 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
01399 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
01400
01401 for (i = 0; i < chip->ecc.total; i++)
01402 chip->oob_poi[eccpos[i]] = ecc_calc[i];
01403
01404 nand_write_page_raw(mtd, chip, buf);
01405 }
01406
01413 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
01414 const uint8_t *buf)
01415 {
01416 int i, eccsize = chip->ecc.size;
01417 int eccbytes = chip->ecc.bytes;
01418 int eccsteps = chip->ecc.steps;
01419 uint8_t *ecc_calc = chip->buffers->ecccalc;
01420 const uint8_t *p = buf;
01421 int *eccpos = chip->ecc.layout->eccpos;
01422
01423 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
01424 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
01425 chip->write_buf(mtd, p, eccsize);
01426 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
01427 }
01428
01429 for (i = 0; i < chip->ecc.total; i++)
01430 chip->oob_poi[eccpos[i]] = ecc_calc[i];
01431
01432 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
01433 }
01434
01444 static void nand_write_page_syndrome(struct mtd_info *mtd,
01445 struct nand_chip *chip, const uint8_t *buf)
01446 {
01447 int i, eccsize = chip->ecc.size;
01448 int eccbytes = chip->ecc.bytes;
01449 int eccsteps = chip->ecc.steps;
01450 const uint8_t *p = buf;
01451 uint8_t *oob = chip->oob_poi;
01452
01453 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
01454
01455 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
01456 chip->write_buf(mtd, p, eccsize);
01457
01458 if (chip->ecc.prepad) {
01459 chip->write_buf(mtd, oob, chip->ecc.prepad);
01460 oob += chip->ecc.prepad;
01461 }
01462
01463 chip->ecc.calculate(mtd, p, oob);
01464 chip->write_buf(mtd, oob, eccbytes);
01465 oob += eccbytes;
01466
01467 if (chip->ecc.postpad) {
01468 chip->write_buf(mtd, oob, chip->ecc.postpad);
01469 oob += chip->ecc.postpad;
01470 }
01471 }
01472
01473
01474 i = mtd->oobsize - (oob - chip->oob_poi);
01475 if (i)
01476 chip->write_buf(mtd, oob, i);
01477 }
01478
01488 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
01489 const uint8_t *buf, int page, int cached, int raw)
01490 {
01491 int status;
01492
01493 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
01494
01495 if (unlikely(raw))
01496 chip->ecc.write_page_raw(mtd, chip, buf);
01497 else
01498 chip->ecc.write_page(mtd, chip, buf);
01499
01500
01501
01502
01503
01504 cached = 0;
01505
01506 if (!cached || !(chip->options & NAND_CACHEPRG)) {
01507
01508 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
01509 status = chip->waitfunc(mtd, chip);
01510
01511
01512
01513
01514 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
01515 status = chip->errstat(mtd, chip, FL_WRITING, status,
01516 page);
01517
01518 if (status & NAND_STATUS_FAIL)
01519 return -EIO;
01520 } else {
01521 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
01522 status = chip->waitfunc(mtd, chip);
01523 }
01524
01525 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
01526
01527 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
01528
01529 if (chip->verify_buf(mtd, buf, mtd->writesize))
01530 return -EIO;
01531 #endif
01532 return 0;
01533 }
01534
01541 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
01542 struct mtd_oob_ops *ops)
01543 {
01544 size_t len = ops->ooblen;
01545
01546 switch(ops->mode) {
01547
01548 case MTD_OOB_PLACE:
01549 case MTD_OOB_RAW:
01550 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
01551 return oob + len;
01552
01553 case MTD_OOB_AUTO: {
01554 struct nand_oobfree *free = chip->ecc.layout->oobfree;
01555 uint32_t boffs = 0, woffs = ops->ooboffs;
01556 size_t bytes = 0;
01557
01558 for(; free->length && len; free++, len -= bytes) {
01559
01560 if (unlikely(woffs)) {
01561 if (woffs >= free->length) {
01562 woffs -= free->length;
01563 continue;
01564 }
01565 boffs = free->offset + woffs;
01566 bytes = min_t(size_t, len,
01567 (free->length - woffs));
01568 woffs = 0;
01569 } else {
01570 bytes = min_t(size_t, len, free->length);
01571 boffs = free->offset;
01572 }
01573 memcpy(chip->oob_poi + boffs, oob, bytes);
01574 oob += bytes;
01575 }
01576 return oob;
01577 }
01578 default:
01579 BUG();
01580 }
01581 return NULL;
01582 }
01583
01584 #define NOTALIGNED(x) (x & (mtd->writesize-1)) != 0
01585
01594 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
01595 struct mtd_oob_ops *ops)
01596 {
01597 int chipnr, realpage, page, blockmask;
01598 struct nand_chip *chip = mtd->priv;
01599 uint32_t writelen = ops->len;
01600 uint8_t *oob = ops->oobbuf;
01601 uint8_t *buf = ops->datbuf;
01602 int bytes = mtd->writesize;
01603 int ret;
01604
01605 ops->retlen = 0;
01606
01607
01608 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
01609 printk(KERN_NOTICE "nand_write: "
01610 "Attempt to write not page aligned data\n");
01611 return -EINVAL;
01612 }
01613
01614 if (!writelen)
01615 return 0;
01616
01617 chipnr = (int)(to >> chip->chip_shift);
01618 chip->select_chip(mtd, chipnr);
01619
01620
01621 if (nand_check_wp(mtd))
01622 return -EIO;
01623
01624 realpage = (int)(to >> chip->page_shift);
01625 page = realpage & chip->pagemask;
01626 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
01627
01628
01629 if (to <= (chip->pagebuf << chip->page_shift) &&
01630 (chip->pagebuf << chip->page_shift) < (to + ops->len))
01631 chip->pagebuf = -1;
01632
01633 chip->oob_poi = chip->buffers->oobwbuf;
01634
01635 while(1) {
01636 int cached = writelen > bytes && page != blockmask;
01637
01638 if (unlikely(oob))
01639 oob = nand_fill_oob(chip, oob, ops);
01640
01641 ret = chip->write_page(mtd, chip, buf, page, cached,
01642 (ops->mode == MTD_OOB_RAW));
01643 if (ret)
01644 break;
01645
01646 writelen -= bytes;
01647 if (!writelen)
01648 break;
01649
01650 buf += bytes;
01651 realpage++;
01652
01653 page = realpage & chip->pagemask;
01654
01655 if (!page) {
01656 chipnr++;
01657 chip->select_chip(mtd, -1);
01658 chip->select_chip(mtd, chipnr);
01659 }
01660 }
01661
01662 if (unlikely(oob))
01663 memset(chip->oob_poi, 0xff, mtd->oobsize);
01664
01665 ops->retlen = ops->len - writelen;
01666 return ret;
01667 }
01668
01679 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
01680 size_t *retlen, const uint8_t *buf)
01681 {
01682 struct nand_chip *chip = mtd->priv;
01683 int ret;
01684
01685
01686 if ((to + len) > mtd->size)
01687 return -EINVAL;
01688 if (!len)
01689 return 0;
01690
01691 nand_get_device(chip, mtd, FL_WRITING);
01692
01693 chip->ops.len = len;
01694 chip->ops.datbuf = (uint8_t *)buf;
01695 chip->ops.oobbuf = NULL;
01696
01697 ret = nand_do_write_ops(mtd, to, &chip->ops);
01698
01699 *retlen = chip->ops.retlen;
01700
01701 nand_release_device(mtd);
01702
01703 return ret;
01704 }
01705
01714 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
01715 struct mtd_oob_ops *ops)
01716 {
01717 int chipnr, page, status;
01718 struct nand_chip *chip = mtd->priv;
01719
01720 DEBUG(MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
01721 (unsigned int)to, (int)ops->len);
01722
01723
01724 if ((ops->ooboffs + ops->len) > mtd->oobsize) {
01725 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
01726 "Attempt to write past end of page\n");
01727 return -EINVAL;
01728 }
01729
01730 chipnr = (int)(to >> chip->chip_shift);
01731 chip->select_chip(mtd, chipnr);
01732
01733
01734 page = (int)(to >> chip->page_shift);
01735
01736
01737
01738
01739
01740
01741
01742 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
01743
01744
01745 if (nand_check_wp(mtd))
01746 return -EROFS;
01747
01748
01749 if (page == chip->pagebuf)
01750 chip->pagebuf = -1;
01751
01752 chip->oob_poi = chip->buffers->oobwbuf;
01753 memset(chip->oob_poi, 0xff, mtd->oobsize);
01754 nand_fill_oob(chip, ops->oobbuf, ops);
01755 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
01756 memset(chip->oob_poi, 0xff, mtd->oobsize);
01757
01758 if (status)
01759 return status;
01760
01761 ops->retlen = ops->len;
01762
01763 return 0;
01764 }
01765
01772 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
01773 struct mtd_oob_ops *ops)
01774 {
01775 struct nand_chip *chip = mtd->priv;
01776 int ret = -ENOTSUPP;
01777
01778 ops->retlen = 0;
01779
01780
01781 if ((to + ops->len) > mtd->size) {
01782 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
01783 "Attempt read beyond end of device\n");
01784 return -EINVAL;
01785 }
01786
01787 nand_get_device(chip, mtd, FL_WRITING);
01788
01789 switch(ops->mode) {
01790 case MTD_OOB_PLACE:
01791 case MTD_OOB_AUTO:
01792 case MTD_OOB_RAW:
01793 break;
01794
01795 default:
01796 goto out;
01797 }
01798
01799 if (!ops->datbuf)
01800 ret = nand_do_write_oob(mtd, to, ops);
01801 else
01802 ret = nand_do_write_ops(mtd, to, ops);
01803
01804 out:
01805 nand_release_device(mtd);
01806 return ret;
01807 }
01808
01816 static void single_erase_cmd(struct mtd_info *mtd, int page)
01817 {
01818 struct nand_chip *chip = mtd->priv;
01819
01820 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
01821 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
01822 }
01823
01832 static void multi_erase_cmd(struct mtd_info *mtd, int page)
01833 {
01834 struct nand_chip *chip = mtd->priv;
01835
01836 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
01837 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
01838 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
01839 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
01840 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
01841 }
01842
01850 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
01851 {
01852 return nand_erase_nand(mtd, instr, 0);
01853 }
01854
01855 #define BBT_PAGE_MASK 0xffffff3f
01856
01864 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
01865 int allowbbt)
01866 {
01867 int page, len, status, pages_per_block, ret, chipnr;
01868 struct nand_chip *chip = mtd->priv;
01869 int rewrite_bbt[NAND_MAX_CHIPS]={0};
01870 unsigned int bbt_masked_page = 0xffffffff;
01871
01872 DEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
01873 (unsigned int)instr->addr, (unsigned int)instr->len);
01874
01875
01876 if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
01877 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
01878 return -EINVAL;
01879 }
01880
01881
01882 if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
01883 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
01884 "Length not block aligned\n");
01885 return -EINVAL;
01886 }
01887
01888
01889 if ((instr->len + instr->addr) > mtd->size) {
01890 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
01891 "Erase past end of device\n");
01892 return -EINVAL;
01893 }
01894
01895 instr->fail_addr = 0xffffffff;
01896
01897
01898 nand_get_device(chip, mtd, FL_ERASING);
01899
01900
01901 page = (int)(instr->addr >> chip->page_shift);
01902 chipnr = (int)(instr->addr >> chip->chip_shift);
01903
01904
01905 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
01906
01907
01908 chip->select_chip(mtd, chipnr);
01909
01910
01911 if (nand_check_wp(mtd)) {
01912 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
01913 "Device is write protected!!!\n");
01914 instr->state = MTD_ERASE_FAILED;
01915 goto erase_exit;
01916 }
01917
01918
01919
01920
01921
01922
01923
01924 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
01925 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
01926
01927
01928 len = instr->len;
01929
01930 instr->state = MTD_ERASING;
01931
01932 while (len) {
01933
01934
01935
01936 if (nand_block_checkbad(mtd, ((loff_t) page) <<
01937 chip->page_shift, 0, allowbbt)) {
01938 printk(KERN_WARNING "nand_erase: attempt to erase a "
01939 "bad block at page 0x%08x\n", page);
01940 instr->state = MTD_ERASE_FAILED;
01941 goto erase_exit;
01942 }
01943
01944
01945
01946
01947
01948 if (page <= chip->pagebuf && chip->pagebuf <
01949 (page + pages_per_block))
01950 chip->pagebuf = -1;
01951
01952 chip->erase_cmd(mtd, page & chip->pagemask);
01953
01954 status = chip->waitfunc(mtd, chip);
01955
01956
01957
01958
01959
01960 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
01961 status = chip->errstat(mtd, chip, FL_ERASING,
01962 status, page);
01963
01964
01965 if (status & NAND_STATUS_FAIL) {
01966 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
01967 "Failed erase, page 0x%08x\n", page);
01968 instr->state = MTD_ERASE_FAILED;
01969 instr->fail_addr = (page << chip->page_shift);
01970 goto erase_exit;
01971 }
01972
01973
01974
01975
01976
01977 if (bbt_masked_page != 0xffffffff &&
01978 (page & BBT_PAGE_MASK) == bbt_masked_page)
01979 rewrite_bbt[chipnr] = (page << chip->page_shift);
01980
01981
01982 len -= (1 << chip->phys_erase_shift);
01983 page += pages_per_block;
01984
01985
01986 if (len && !(page & chip->pagemask)) {
01987 chipnr++;
01988 chip->select_chip(mtd, -1);
01989 chip->select_chip(mtd, chipnr);
01990
01991
01992
01993
01994
01995 if (bbt_masked_page != 0xffffffff &&
01996 (chip->bbt_td->options & NAND_BBT_PERCHIP))
01997 bbt_masked_page = chip->bbt_td->pages[chipnr] &
01998 BBT_PAGE_MASK;
01999 }
02000 }
02001 instr->state = MTD_ERASE_DONE;
02002
02003 erase_exit:
02004
02005 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
02006
02007 if (!ret)
02008 mtd_erase_callback(instr);
02009
02010
02011 nand_release_device(mtd);
02012
02013
02014
02015
02016
02017 if (bbt_masked_page == 0xffffffff || ret)
02018 return ret;
02019
02020 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
02021 if (!rewrite_bbt[chipnr])
02022 continue;
02023
02024 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
02025 "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
02026 chip->bbt_td->pages[chipnr]);
02027 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
02028 }
02029
02030
02031 return ret;
02032 }
02033
02040 static void nand_sync(struct mtd_info *mtd)
02041 {
02042 struct nand_chip *chip = mtd->priv;
02043
02044 DEBUG(MTD_DEBUG_LEVEL3, "nand_sync: called\n");
02045
02046
02047 nand_get_device(chip, mtd, FL_SYNCING);
02048
02049 nand_release_device(mtd);
02050 }
02051
02057 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
02058 {
02059
02060 if (offs > mtd->size)
02061 return -EINVAL;
02062
02063 return nand_block_checkbad(mtd, offs, 1, 0);
02064 }
02065
02071 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
02072 {
02073 struct nand_chip *chip = mtd->priv;
02074 int ret;
02075
02076 if ((ret = nand_block_isbad(mtd, ofs))) {
02077
02078 if (ret > 0)
02079 return 0;
02080 return ret;
02081 }
02082
02083 return chip->block_markbad(mtd, ofs);
02084 }
02085
02090 static int nand_suspend(struct mtd_info *mtd)
02091 {
02092 struct nand_chip *chip = mtd->priv;
02093
02094 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
02095 }
02096
02101 static void nand_resume(struct mtd_info *mtd)
02102 {
02103 struct nand_chip *chip = mtd->priv;
02104
02105 if (chip->state == FL_PM_SUSPENDED)
02106 nand_release_device(mtd);
02107 else
02108 printk(KERN_ERR "nand_resume() called for a chip which is not "
02109 "in suspended state\n");
02110 }
02111
02112
02113
02114
02115 static void nand_set_defaults(struct nand_chip *chip, int busw)
02116 {
02117
02118 if (!chip->chip_delay)
02119 chip->chip_delay = 20;
02120
02121
02122 if (chip->cmdfunc == NULL)
02123 chip->cmdfunc = nand_command;
02124
02125
02126 if (chip->waitfunc == NULL)
02127 chip->waitfunc = nand_wait;
02128
02129 if (!chip->select_chip)
02130 chip->select_chip = nand_select_chip;
02131 if (!chip->read_byte)
02132 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
02133 if (!chip->read_word)
02134 chip->read_word = nand_read_word;
02135 if (!chip->block_bad)
02136 chip->block_bad = nand_block_bad;
02137 if (!chip->block_markbad)
02138 chip->block_markbad = nand_default_block_markbad;
02139 if (!chip->write_buf)
02140 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
02141 if (!chip->read_buf)
02142 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
02143 if (!chip->verify_buf)
02144 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
02145 if (!chip->scan_bbt)
02146 chip->scan_bbt = nand_default_bbt;
02147
02148 if (!chip->controller) {
02149 chip->controller = &chip->hwcontrol;
02150 spin_lock_init(&chip->controller->lock);
02151 init_waitqueue_head(&chip->controller->wq);
02152 }
02153
02154 }
02155
02156
02157
02158
02159 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
02160 struct nand_chip *chip,
02161 int busw, int *maf_id)
02162 {
02163 struct nand_flash_dev *type = NULL;
02164 int i, dev_id, maf_idx;
02165
02166 unsigned char * dev_ids= (unsigned char * ) &(chip->full_id);
02167
02168
02169 chip->select_chip(mtd, 0);
02170
02171
02172 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
02173
02174
02175 dev_ids[0]=*maf_id = chip->read_byte(mtd);
02176 dev_ids[1]=dev_id = chip->read_byte(mtd);
02177
02178
02179 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
02180 if (dev_id == nand_flash_ids[i].id) {
02181 type = &nand_flash_ids[i];
02182 break;
02183 }
02184 }
02185
02186 if (!type)
02187 return ERR_PTR(-ENODEV);
02188
02189 if (!mtd->name)
02190 mtd->name = type->name;
02191
02192 chip->chipsize = type->chipsize << 20;
02193
02194
02195 if (!type->pagesize) {
02196 int extid;
02197
02198 dev_ids[2]= extid = chip->read_byte(mtd);
02199
02200 dev_ids[3]= extid = chip->read_byte(mtd);
02201
02202 mtd->writesize = 1024 << (extid & 0x3);
02203 extid >>= 2;
02204
02205 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
02206 extid >>= 2;
02207
02208 mtd->erasesize = (64 * 1024) << (extid & 0x03);
02209 extid >>= 2;
02210
02211 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
02212
02213 } else {
02214
02215
02216
02217 mtd->erasesize = type->erasesize;
02218 mtd->writesize = type->pagesize;
02219 mtd->oobsize = mtd->writesize / 32;
02220 busw = type->options & NAND_BUSWIDTH_16;
02221 }
02222
02223
02224 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
02225 if (nand_manuf_ids[maf_idx].id == *maf_id)
02226 break;
02227 }
02228
02229
02230
02231
02232
02233 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
02234 printk(KERN_INFO "NAND device: Manufacturer ID:"
02235 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
02236 dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
02237 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
02238 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
02239 busw ? 16 : 8);
02240 return ERR_PTR(-EINVAL);
02241 }
02242
02243
02244 chip->page_shift = ffs(mtd->writesize) - 1;
02245
02246 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
02247
02248 chip->bbt_erase_shift = chip->phys_erase_shift =
02249 ffs(mtd->erasesize) - 1;
02250 chip->chip_shift = ffs(chip->chipsize) - 1;
02251
02252
02253 chip->badblockpos = mtd->writesize > 512 ?
02254 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
02255
02256
02257 chip->options &= ~NAND_CHIPOPTIONS_MSK;
02258 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
02259
02260
02261
02262
02263 chip->options |= NAND_NO_AUTOINCR;
02264
02265
02266
02267
02268 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
02269 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
02270
02271
02272 if (chip->options & NAND_4PAGE_ARRAY)
02273 chip->erase_cmd = multi_erase_cmd;
02274 else
02275 chip->erase_cmd = single_erase_cmd;
02276
02277
02278 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
02279 chip->cmdfunc = nand_command_lp;
02280
02281 printk(KERN_INFO "NAND device: Manufacturer ID:"
02282 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
02283 nand_manuf_ids[maf_idx].name, type->name);
02284 printk (KERN_INFO "Additional Info: ID byte3=0x%x, byte4=0x%x\n", dev_ids[2], dev_ids[3]);
02285
02286
02287 return type;
02288 }
02289
02300 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
02301 {
02302 int i, busw, nand_maf_id;
02303 struct nand_chip *chip = mtd->priv;
02304 struct nand_flash_dev *type;
02305
02306
02307 busw = chip->options & NAND_BUSWIDTH_16;
02308
02309 nand_set_defaults(chip, busw);
02310
02311
02312 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
02313
02314 if (IS_ERR(type)) {
02315 printk(KERN_WARNING "No NAND device found!!!\n");
02316 chip->select_chip(mtd, -1);
02317 return PTR_ERR(type);
02318 }
02319
02320
02321 for (i = 1; i < maxchips; i++) {
02322 chip->select_chip(mtd, i);
02323
02324 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
02325
02326 if (nand_maf_id != chip->read_byte(mtd) ||
02327 type->id != chip->read_byte(mtd))
02328 break;
02329 }
02330 if (i > 1)
02331 printk(KERN_INFO "%d NAND chips detected\n", i);
02332
02333
02334 chip->numchips = i;
02335 mtd->size = i * chip->chipsize;
02336
02337 return 0;
02338 }
02339
02340
02350 int nand_scan_tail(struct mtd_info *mtd)
02351 {
02352 int i;
02353 struct nand_chip *chip = mtd->priv;
02354
02355 if (!(chip->options & NAND_OWN_BUFFERS))
02356 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
02357 if (!chip->buffers)
02358 return -ENOMEM;
02359
02360
02361 memset(chip->buffers->oobwbuf, 0xff, mtd->oobsize);
02362
02363
02364
02365
02366 if (!chip->ecc.layout) {
02367 switch (mtd->oobsize) {
02368 case 8:
02369 chip->ecc.layout = &nand_oob_8;
02370 break;
02371 case 16:
02372 chip->ecc.layout = &nand_oob_16;
02373 break;
02374 case 64:
02375 chip->ecc.layout = &nand_oob_64;
02376 break;
02377 default:
02378 printk(KERN_WARNING "No oob scheme defined for "
02379 "oobsize %d\n", mtd->oobsize);
02380 BUG();
02381 }
02382 }
02383
02384 if (!chip->write_page)
02385 chip->write_page = nand_write_page;
02386
02387
02388
02389
02390
02391 if (!chip->ecc.read_page_raw)
02392 chip->ecc.read_page_raw = nand_read_page_raw;
02393 if (!chip->ecc.write_page_raw)
02394 chip->ecc.write_page_raw = nand_write_page_raw;
02395
02396 switch (chip->ecc.mode) {
02397 case NAND_ECC_HW:
02398
02399 if (!chip->ecc.read_page)
02400 chip->ecc.read_page = nand_read_page_hwecc;
02401 if (!chip->ecc.write_page)
02402 chip->ecc.write_page = nand_write_page_hwecc;
02403 if (!chip->ecc.read_oob)
02404 chip->ecc.read_oob = nand_read_oob_std;
02405 if (!chip->ecc.write_oob)
02406 chip->ecc.write_oob = nand_write_oob_std;
02407
02408 case NAND_ECC_HW_SYNDROME:
02409 if (!chip->ecc.calculate || !chip->ecc.correct ||
02410 !chip->ecc.hwctl) {
02411 printk(KERN_WARNING "No ECC functions supplied, "
02412 "Hardware ECC not possible\n");
02413 BUG();
02414 }
02415
02416 if (!chip->ecc.read_page)
02417 chip->ecc.read_page = nand_read_page_syndrome;
02418 if (!chip->ecc.write_page)
02419 chip->ecc.write_page = nand_write_page_syndrome;
02420 if (!chip->ecc.read_oob)
02421 chip->ecc.read_oob = nand_read_oob_syndrome;
02422 if (!chip->ecc.write_oob)
02423 chip->ecc.write_oob = nand_write_oob_syndrome;
02424
02425 if (mtd->writesize >= chip->ecc.size)
02426 break;
02427 printk(KERN_WARNING "%d byte HW ECC not possible on "
02428 "%d byte page size, fallback to SW ECC\n",
02429 chip->ecc.size, mtd->writesize);
02430 chip->ecc.mode = NAND_ECC_SOFT;
02431
02432 case NAND_ECC_SOFT:
02433 chip->ecc.calculate = nand_calculate_ecc;
02434 chip->ecc.correct = nand_correct_data;
02435 chip->ecc.read_page = nand_read_page_swecc;
02436 chip->ecc.write_page = nand_write_page_swecc;
02437 chip->ecc.read_oob = nand_read_oob_std;
02438 chip->ecc.write_oob = nand_write_oob_std;
02439 chip->ecc.size = 256;
02440 chip->ecc.bytes = 3;
02441 break;
02442
02443 case NAND_ECC_NONE:
02444 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
02445 "This is not recommended !!\n");
02446 chip->ecc.read_page = nand_read_page_raw;
02447 chip->ecc.write_page = nand_write_page_raw;
02448 chip->ecc.read_oob = nand_read_oob_std;
02449 chip->ecc.write_oob = nand_write_oob_std;
02450 chip->ecc.size = mtd->writesize;
02451 chip->ecc.bytes = 0;
02452 break;
02453
02454 default:
02455 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
02456 chip->ecc.mode);
02457 BUG();
02458 }
02459
02460
02461
02462
02463
02464 chip->ecc.layout->oobavail = 0;
02465 for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
02466 chip->ecc.layout->oobavail +=
02467 chip->ecc.layout->oobfree[i].length;
02468
02469
02470
02471
02472
02473 chip->ecc.steps = mtd->writesize / chip->ecc.size;
02474 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
02475 printk(KERN_WARNING "Invalid ecc parameters\n");
02476 BUG();
02477 }
02478 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
02479
02480
02481 chip->state = FL_READY;
02482
02483
02484 chip->select_chip(mtd, -1);
02485
02486
02487 chip->pagebuf = -1;
02488
02489
02490 mtd->type = MTD_NANDFLASH;
02491 mtd->flags = MTD_CAP_NANDFLASH;
02492 mtd->ecctype = MTD_ECC_SW;
02493 mtd->erase = nand_erase;
02494 mtd->point = NULL;
02495 mtd->unpoint = NULL;
02496 mtd->read = nand_read;
02497 mtd->write = nand_write;
02498 mtd->read_oob = nand_read_oob;
02499 mtd->write_oob = nand_write_oob;
02500 mtd->sync = nand_sync;
02501 mtd->lock = NULL;
02502 mtd->unlock = NULL;
02503 mtd->suspend = nand_suspend;
02504 mtd->resume = nand_resume;
02505 mtd->block_isbad = nand_block_isbad;
02506 mtd->block_markbad = nand_block_markbad;
02507
02508
02509 mtd->ecclayout = chip->ecc.layout;
02510
02511
02512 if (chip->options & NAND_SKIP_BBTSCAN)
02513 return 0;
02514
02515
02516 return chip->scan_bbt(mtd);
02517 }
02518
02519
02520
02521
02522 #ifdef MODULE
02523 #define caller_is_module() (1)
02524 #else
02525 #define caller_is_module() \
02526 module_text_address((unsigned long)__builtin_return_address(0))
02527 #endif
02528
02541 int nand_scan(struct mtd_info *mtd, int maxchips)
02542 {
02543 int ret;
02544
02545
02546 if (!mtd->owner && caller_is_module()) {
02547 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
02548 BUG();
02549 }
02550
02551 ret = nand_scan_ident(mtd, maxchips);
02552 if (!ret)
02553 ret = nand_scan_tail(mtd);
02554 return ret;
02555 }
02556
02561 void nand_release(struct mtd_info *mtd)
02562 {
02563 struct nand_chip *chip = mtd->priv;
02564
02565 #ifdef CONFIG_MTD_PARTITIONS
02566
02567 del_mtd_partitions(mtd);
02568 #endif
02569
02570 del_mtd_device(mtd);
02571
02572
02573 kfree(chip->bbt);
02574 if (!(chip->options & NAND_OWN_BUFFERS))
02575 kfree(chip->buffers);
02576 }
02577
02578 EXPORT_SYMBOL_GPL(nand_scan);
02579 EXPORT_SYMBOL_GPL(nand_scan_ident);
02580 EXPORT_SYMBOL_GPL(nand_scan_tail);
02581 EXPORT_SYMBOL_GPL(nand_release);
02582
02583 static int __init nand_base_init(void)
02584 {
02585 led_trigger_register_simple("nand-disk", &nand_led_trigger);
02586 return 0;
02587 }
02588
02589 static void __exit nand_base_exit(void)
02590 {
02591 led_trigger_unregister_simple(nand_led_trigger);
02592 }
02593
02594 module_init(nand_base_init);
02595 module_exit(nand_base_exit);
02596
02597 MODULE_LICENSE("GPL");
02598 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
02599 MODULE_DESCRIPTION("Generic NAND flash driver code");