os/linux-2.6-tag--devboard-R2_10-4/arch/cris/arch-v32/drivers/nandflash.c

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/*
 *  arch/cris/arch-v32/drivers/nandflash.c
 *
 *  Copyright (c) 2004
 *
 *  Derived from drivers/mtd/nand/spia.c
 *        Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
 * 
 * $Id: nandflash.c,v 1.1.1.1 2008/11/27 20:04:00 elphel Exp $
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/slab.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <asm/arch/memmap.h>
#include <asm/arch/hwregs/reg_map.h>
#include <asm/arch/hwregs/reg_rdwr.h>
#include <asm/arch/hwregs/gio_defs.h>
#include <asm/arch/hwregs/bif_core_defs.h>
#include <asm/io.h>
#include <linux/time.h> //debug - AF


#define CE_BIT 4
#define CLE_BIT 5
#define ALE_BIT 6
#define BY_BIT 7

/* Bitmask for control pins */
#define PIN_BITMASK ((1 << CE_BIT) | (1 << CLE_BIT) | (1 << ALE_BIT))

/* Bitmask for mtd nand control bits */
#define CTRL_BITMASK (NAND_NCE | NAND_CLE | NAND_ALE)

#define DEBUG_ELPHEL_MTD 1
static struct mtd_info *crisv32_mtd = NULL;
/* 
 *      hardware specific access to control-lines
*/

volatile unsigned long *port_dummy_addr; 


static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd,
                              unsigned int ctrl)
{
//   unsigned long flags;
   reg_gio_rw_pa_dout dout;
   struct nand_chip *this = mtd->priv;
#if DEBUG_ELPHEL_MTD
   reg_bif_core_rw_grp3_cfg csr3_cfg=REG_RD(bif_core, regi_bif_core, rw_grp3_cfg);
   int dd=((int *) &csr3_cfg)[0];
   int dbg_mark=0;
#endif
//      local_irq_save(flags);
        /* control bits change */
   if (ctrl & NAND_CTRL_CHANGE) {
     dout = REG_RD(gio, regi_gio, rw_pa_dout);
#if DEBUG_ELPHEL_MTD
     if (dd & 0x10000000)  dbg_mark= (dout.data & (1 << CE_BIT)) && (ctrl & NAND_NCE);
#endif
     dout.data &= ~PIN_BITMASK;
#if (CE_BIT == 4 && NAND_NCE == 1 &&  \
     CLE_BIT == 5 && NAND_CLE == 2 && \
     ALE_BIT == 6 && NAND_ALE == 4)
                /* Pins in same order as control bits, but shifted.
                 * Optimize for this case; works for 2.6.18 */
      if (!(ctrl & NAND_NCE)) ctrl &= ~(NAND_ALE | NAND_CLE); // Andrey - same as in bootloader, turn off ALE, CLE if no CE. Optimize if works
                dout.data |= ((ctrl & CTRL_BITMASK) ^ NAND_NCE) << CE_BIT;
#warning using FAST nand bits =================================, yes, here
#else
                /* the slow way */
                if (!(ctrl & NAND_NCE))
                        dout.data |= (1 << CE_BIT);
                if (ctrl & NAND_CLE)
                        dout.data |= (1 << CLE_BIT);
                if (ctrl & NAND_ALE)
                        dout.data |= (1 << ALE_BIT);
#warning using SLOW nand bits =================================
#endif
      REG_WR(gio, regi_gio, rw_pa_dout, dout);
        }
#if DEBUG_ELPHEL_MTD
   if (dbg_mark) printk("}");
#endif

        /* command to chip */
        if (cmd != NAND_CMD_NONE) {
                writeb(cmd, this->IO_ADDR_W);
//      if (port_dummy_addr[0]) {  local_irq_restore(flags) };
//      else                    {  local_irq_restore(flags) };
      if (port_dummy_addr[0]) return;
      return;
   }
//      local_irq_restore(flags);
}

/*
*       read device ready pin
*/
int crisv32_device_ready(struct mtd_info *mtd)
{
   reg_gio_rw_pa_dout dout; //AF
   dout = REG_RD(gio, regi_gio, rw_pa_dout); // AF
   if (dout.data & NAND_NCE) printk("probed READY while NCE==1 !!!\n");
//printk("R"); // command
        reg_gio_r_pa_din din = REG_RD(gio, regi_gio, r_pa_din);
        return ((din.data & (1 << BY_BIT)) >> BY_BIT);
}

/*
 * Main initialization routine
 */
struct mtd_info* __init crisv32_nand_flash_probe (void)
{
        void __iomem *read_cs;
        void __iomem *write_cs;

        reg_bif_core_rw_grp3_cfg bif_cfg = REG_RD(bif_core, regi_bif_core, rw_grp3_cfg);
        reg_gio_rw_pa_oe pa_oe = REG_RD(gio, regi_gio, rw_pa_oe);
        struct nand_chip *this;
        int err = 0;

        /* Allocate memory for MTD device structure and private data */
        crisv32_mtd = kmalloc (sizeof(struct mtd_info) + sizeof (struct nand_chip),
                                GFP_KERNEL);
        if (!crisv32_mtd) {
                printk ("Unable to allocate CRISv32 NAND MTD device structure.\n");
                err = -ENOMEM;
                return NULL;
        }

        read_cs   = ioremap(MEM_CSP0_START | MEM_NON_CACHEABLE, 8192);
        write_cs  = ioremap(MEM_CSP1_START | MEM_NON_CACHEABLE, 8192);

        if (!read_cs || !write_cs) {
                printk("CRISv32 NAND ioremap failed\n");
                err = -EIO;
                goto out_mtd;
        }
   port_dummy_addr= (unsigned long *) ioremap(MEM_CSR1_START | MEM_NON_CACHEABLE, 8192);
   if (!port_dummy_addr) {
      printk("CRISv32 NAND - port_dummy_addr ioremap failed\n");
      err = -EIO;
      goto out_dummy;
   }

        /* Get pointer to private data */
        this = (struct nand_chip *) (&crisv32_mtd[1]);

        pa_oe.oe |= 1 << CE_BIT;
        pa_oe.oe |= 1 << ALE_BIT;
        pa_oe.oe |= 1 << CLE_BIT;
        pa_oe.oe &= ~ (1 << BY_BIT);
        REG_WR(gio, regi_gio, rw_pa_oe, pa_oe);

        bif_cfg.gated_csp0 = regk_bif_core_rd;
        bif_cfg.gated_csp1 = regk_bif_core_wr;
        REG_WR(bif_core, regi_bif_core, rw_grp3_cfg, bif_cfg);

        /* Initialize structures */
        memset((char *) crisv32_mtd, 0, sizeof(struct mtd_info));
        memset((char *) this, 0, sizeof(struct nand_chip));

        /* Link the private data with the MTD structure */
        crisv32_mtd->priv = this;

        /* Set address of NAND IO lines */
        this->IO_ADDR_R = read_cs;
        this->IO_ADDR_W = write_cs;
        this->cmd_ctrl = crisv32_hwcontrol;
        this->dev_ready = crisv32_device_ready;
        /* 20 us command delay time */
        this->chip_delay = 20;          
        this->ecc.mode = NAND_ECC_SOFT;

        /* Enable the following for a flash based bad block table */
        /* this->options = NAND_USE_FLASH_BBT; */
        this->options = NAND_USE_FLASH_BBT;

        /* Scan to find existance of the device */
        if (nand_scan (crisv32_mtd, 1)) {
                err = -ENXIO;
                goto out_ior;
        }
   int isg=0;
   int old= ((int *) &bif_cfg)[0];
   switch ((((this->full_id) >> 24) & 0xff) & 0x88) {
   case 0x00: isg=50; //cycle 50ns
      bif_cfg.lw=3;
      bif_cfg.ew=1;
      bif_cfg.zw=1;
      break;
   case 0x08: isg=30; //cycle 30ns
      bif_cfg.lw=1;
      bif_cfg.ew=0; 
      bif_cfg.zw=0;
      break;
   case 0x80: isg=25; //cycle 25ns
      bif_cfg.lw=0;
      bif_cfg.ew=0;
      bif_cfg.zw=0;
      break;
   default: isg=-1; // reserved
   };
   if (isg>=0) {
     printk ("Flash is rated %d ns, modifying bif_core_rw_grp3: old=0x%x, new=0x%x\n",isg,old, ((int *) &bif_cfg)[0]);
     REG_WR(bif_core, regi_bif_core, rw_grp3_cfg, bif_cfg);
   } else printk ("Unrecognised flash speed grade - ID3=0x%02x\n",(int) ((this->full_id) >> 24) & 0xff);

        return crisv32_mtd;
        
out_ior:
   iounmap((void *) port_dummy_addr);
out_dummy:
        iounmap((void *) read_cs);
        iounmap((void *) write_cs);     
out_mtd:
        kfree (crisv32_mtd);
        return NULL;
}

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