modules/usb/iop/common-R1_01/iop-usb.c

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/* $Id: iop-usb.c,v 1.1.1.1 2008/11/27 20:04:03 elphel Exp $
 *
 * ETRAX FS IOP USB 1.1 Host Controller
 *
 * Initialization of hardware and interaction with IOP
 *
 * Copyright (C) 2004, 2005  Axis Communications AB
 *
 * Author: Lars Viklund <larsv@axis.com>
 */

#include "compat.h"
#include <asm/arch/hwregs/intr_vect.h>
#include <asm/arch/hwregs/dma_defs.h>
#include <asm/arch/hwregs/iop/iop_reg_space.h>
#include <asm/arch/hwregs/iop/iop_mpu_macros.h>
#include <asm/arch/hwregs/iop/iop_mpu_defs.h>
#include <asm/arch/hwregs/iop/iop_spu_defs.h>
#include <asm/arch/hwregs/iop/iop_sw_cfg_defs.h>
#include <asm/arch/hwregs/iop/iop_sw_cpu_defs.h>
#include <asm/arch/hwregs/iop/iop_dmc_in_defs.h>
#include <asm/arch/hwregs/iop/iop_fifo_in_defs.h>
#include <asm/arch/hwregs/iop/iop_fifo_out_defs.h>
#include <asm/arch/hwregs/iop/iop_scrc_out_defs.h>
#include <asm/arch/hwregs/iop/iop_crc_par_defs.h>
#include <asm/arch/hwregs/iop/iop_sap_in_defs.h>
#include <asm/arch/hwregs/iop/iop_sap_out_defs.h>
#include <asm/arch/hwregs/iop/iop_timer_grp_defs.h>
#include "iop-usb.h"
#include "iop-usb-int.h"

#ifdef SIMDEF_TARGET_BANANA
#define D(x)                    (x)
#else /* SIMDEF_TARGET_BANANA */
#define D(x)
#endif /* SIMDEF_TARGET_BANANA */

/* number of iteration in before timeout while waiting for IOP */
#define IOP_TIMEOUT             1000

/* port status power state */
static unsigned int port_power; 

/* convert output context descriptor to endpoint descriptor (depends
 * on this descriptor being the first field in struct iop_usb_ed) */
static __inline__ struct iop_usb_ed *ctxt_to_ed(dma_descr_context *ctxt)
{
        return (struct iop_usb_ed *) ctxt;
}

/* 
 * The constants for maxium interval for periodic traffic below may
 * be adjusted as needed. However, note that the Linux USB core
 * currently does not allow value larger than 255 for interrupt
 * traffic and 1024 for isochronous traffic.
 */

/* maximum interval for isochronous traffic */
#define MAX_INTERVAL_ISOC       1024

/* maximum interval for interrupt traffic */
#define MAX_INTERVAL_INTR       256

/* total number of transfer types */
#define NUM_TRANSFER_TYPE       4

/* number of periodic transfer types */
#define NUM_PER_TRANSFER_TYPE   2

/* extra group descriptor with EOL */
#define IOP_USB_GROUP_EOL       (IOP_USB_BULK + 1)

/* DMA group descriptors */
static dma_descr_group *group_top;
static dma_descr_group *group_head;
static struct {
        int num;
        dma_descr_group *groups;
} group_periodic[NUM_PER_TRANSFER_TYPE];
static unsigned long group_top_phys;

/* DMA context descriptors */
static dma_descr_context *ctxt_head;
static dma_descr_context *ctxt_eol;
static dma_descr_context *ctxt_in_eol;

/* total allocation size for static DMA descriptors */
#define TOTAL_DESCR_SIZE ( \
        (sizeof(dma_descr_context) * \
         (NUM_TRANSFER_TYPE + NUM_PER_TRANSFER_TYPE + 2)) + \
        (sizeof(dma_descr_group) * \
         (1 + NUM_TRANSFER_TYPE + 1 + MAX_INTERVAL_ISOC + MAX_INTERVAL_INTR)) \
        )

/* dummy buffer, for overflow input data */
#define DUMMY_BUF_SIZE          1500 /* largest possible packet in one frame */
static char *dummy_buf;              /* physical address of dummy buffer */

/* allocate dummy buffer */
static int alloc_dummy_buf(void)
{
        DUMMY_BUF(buf, DUMMY_BUF_SIZE);

        if (!buf)
                return -1;
        dummy_buf = buf;
        return 0;
}

/* allocate static DMA descriptors */

static char *cur_static_descr;

static __inline__ int init_alloc_static_descr(void)
{
        STATIC_DMA_DESCR(buf, TOTAL_DESCR_SIZE, L1_CACHE_BYTES);
        if (!buf)
                return -1;
        cur_static_descr = buf;
        return 0;
}

static __inline__ void* alloc_static_descr(size_t size)
{
        void *descr = cur_static_descr;
        cur_static_descr += size;
        return descr;
}

#define ALLOC_DESCR(num, type) \
        ((type *) alloc_static_descr((num) * sizeof(type)))

static int alloc_static_descrs(void)
{
        if (init_alloc_static_descr() != 0)
                return -1;

        ctxt_head =     ALLOC_DESCR(NUM_TRANSFER_TYPE, dma_descr_context);
        ctxt_eol =      ALLOC_DESCR(NUM_PER_TRANSFER_TYPE, dma_descr_context);
        ctxt_in_eol =   ALLOC_DESCR(2, dma_descr_context);
        group_top =     ALLOC_DESCR(1, dma_descr_group);
        group_head =    ALLOC_DESCR(NUM_TRANSFER_TYPE + 1, dma_descr_group);

        group_periodic[IOP_USB_ISOC].num = MAX_INTERVAL_ISOC;
        group_periodic[IOP_USB_ISOC].groups = 
                ALLOC_DESCR(MAX_INTERVAL_ISOC, dma_descr_group);

        group_periodic[IOP_USB_INTR].num = MAX_INTERVAL_INTR;
        group_periodic[IOP_USB_INTR].groups =
                ALLOC_DESCR(MAX_INTERVAL_INTR, dma_descr_group);

        return 0;
}

/* initialize DMA data structure for periodic traffic */
static void init_dma_periodic(enum iop_usb_transaction_type type)
{
        unsigned int i, num_groups = group_periodic[type].num;
        dma_descr_group *groups = group_periodic[type].groups;

        for (i = 0; i < num_groups; i++) {
                struct iop_usb_ttd *ttd = iop_usb_ttd(&groups[i]);
                memset(&groups[i], 0, sizeof(dma_descr_group));
                groups[i].bol = 1; 
                groups[i].up = VIRT_TO_PHYS(&group_head[type]);
                groups[i].next = 
                        VIRT_TO_PHYS(&groups[i > 0 ? i - 1 : num_groups - 1]);
                groups[i].down.context = VIRT_TO_PHYS(&ctxt_head[type]);
                ttd->is_periodic = 1;
                ttd->is_isoc = type == IOP_USB_ISOC;    
        }
        memset(&ctxt_eol[type], 0, sizeof(dma_descr_context));
        ctxt_eol[type].eol = 1;
        ctxt_eol[type].store_mode = 1;
        ctxt_eol[type].next = VIRT_TO_PHYS(&ctxt_head[type]);
}

/* initialize DMA descriptors used to terminate input context
 * descriptor lists */
static void init_dma_in(void) 
{
        int i;

        for (i = 0; i < 2; i++) {
                memset(&ctxt_in_eol[i], 0, sizeof(dma_descr_context));
                ctxt_in_eol->eol = 1;
                ctxt_in_eol->next = VIRT_TO_PHYS(&ctxt_in_eol[(i + 1) % 2]);
        }
}

/* initialize DMA data structure and enable DMA */
static void init_dma(void)
{
        unsigned int type;

        group_top_phys = (unsigned long) VIRT_TO_PHYS(group_top);
        memset(group_top, 0, sizeof(dma_descr_group));
        group_top->tol = 1;
        group_top->bol = 1;
        group_top->eol = 1;
        group_top->next = VIRT_TO_PHYS(&group_head[IOP_USB_ISOC]);

        for (type = 0; type <= NUM_TRANSFER_TYPE; type++) {
                struct iop_usb_ttd *ttd_head = iop_usb_ttd(&group_head[type]);

                memset(&group_head[type], 0, sizeof(dma_descr_group));
                group_head[type].up = VIRT_TO_PHYS(group_top);

                if (type != IOP_USB_GROUP_EOL)
                        memset(&ctxt_head[type], 0, sizeof(dma_descr_context));

                switch (type) {
                case IOP_USB_ISOC:
                        ttd_head->is_isoc = 1;
                        /*FALLTHROUGH*/
                case IOP_USB_INTR:
                        ttd_head->is_periodic = 1;
                        group_head[type].down.group = 
                                VIRT_TO_PHYS(group_periodic[type].groups);
                        ctxt_head[type].next = 
                                VIRT_TO_PHYS(&ctxt_eol[type]);
                        break;
                case IOP_USB_CTRL:
                        ttd_head->is_ctrl = 1;
                        /*FALLTHROUGH*/
                case IOP_USB_BULK:
                        group_head[type].bol = 1;
                        group_head[type].down.context =
                                VIRT_TO_PHYS(&ctxt_head[type]);
                        ctxt_head[type].next = 
                                VIRT_TO_PHYS(&ctxt_head[type]);
                        break;
                case IOP_USB_GROUP_EOL:
                        group_head[type].next = VIRT_TO_PHYS(group_top);
                        group_head[type].bol = 1;
                        group_head[type].eol = 1;
                        continue;
                default:
                        BUG();
                }

                group_head[type].next = VIRT_TO_PHYS(&group_head[type + 1]);
                ctxt_head[type].eol = 1;
                ctxt_head[type].store_mode = 1;
        }

        init_dma_periodic(IOP_USB_ISOC);
        init_dma_periodic(IOP_USB_INTR);
        init_dma_in();

        wmb();

        DMA_RESET(INST(dma_out));
        DMA_ENABLE(INST(dma_out));
        REG_WR(dma, INST(dma_out), rw_group, group_top_phys);
        REG_WR(dma, INST(dma_out), rw_ctxt, 0);
        REG_WR(dma, INST(dma_out), rw_ctxt_next, 0);
        DMA_WR_CMD(INST(dma_out), regk_dma_load_g);
        
        DMA_RESET(INST(dma_in));
        DMA_ENABLE(INST(dma_in));
        DMA_WR_CMD(INST(dma_in), regk_dma_set_w_size1);
}

/* enable group, called when data has been inserted */
static __inline__ void enable_group(enum iop_usb_transfer_type type)
{
        wmb();
        group_head[type].en =  1;
        group_head[type].dis = 0;
}

/* reset the status of an endpoint, called when clearing an error condition */
static __inline__ void reset_ed_status(struct iop_usb_ed *ed)
{
        struct iop_usb_ctxt_md *ctxt_md = iop_usb_ctxt_md(&ed->ctxt);
        ctxt_md->stat = IOP_USB_STAT_OK;
        ctxt_md->toggle = 0;
}

/* reset output context pointers to data */
static void reset_out_context(struct iop_usb_ed *ed, struct iop_usb_td *td)
{
        dma_descr_context *ctxt = &ed->ctxt;
 
        BUG_ON(ctxt->en && !ctxt->dis);

        if (!td) {
                ctxt->saved_data = NULL;
                ctxt->saved_data_buf = NULL;
                return;
        }
        ctxt->saved_data = VIRT_TO_PHYS(&td->u.priv.d_out);
        ctxt->saved_data_buf = td->u.priv.d_out.buf;
        wmb();
        ctxt->dis = 0;
}

/* busy-wait until the DMA is clear of this (disabled) context */
static void wait_on_ctxt(struct iop_usb_ed *ed)
{
        unsigned int type = ed->type; 
        unsigned long phys = (unsigned long) VIRT_TO_PHYS(&ed->ctxt);
        unsigned long group_first, group_last;
        reg_dma_rw_stat stat;

        BUG_ON(ed->ctxt.en);

        if (type == IOP_USB_ISOC || type == IOP_USB_INTR) {
                group_first = (unsigned int) 
                        VIRT_TO_PHYS(group_periodic[type].groups);
                group_last = group_first + (group_periodic[type].num - 1 ) * 
                        sizeof(dma_descr_group *);
        } else
                group_first = group_last = (unsigned int)
                        VIRT_TO_PHYS(&group_head[type]);
        wmb(); /* for write which disables context */
        while (((REG_RD(dma, INST(dma_out), rw_group) >= group_first) &&
                (REG_RD(dma, INST(dma_out), rw_group) <= group_last)) &&
               ((phys == REG_RD(dma, INST(dma_out), rw_ctxt)          ||
                 phys == REG_RD(dma, INST(dma_out), rw_ctxt_next)     ||
                 phys == REG_RD(dma, INST(dma_out), rw_group_down)))) {
                stat = REG_RD(dma, INST(dma_out), rw_stat);
                if (stat.mode != regk_dma_running)
                        break;
                BUSY_WAIT();
        }
}

/* adjust group descriptor down pointers for periodic traffic */
static void schedule_periodic(unsigned int type, dma_descr_context *ctxt)
{
        unsigned int i, num = group_periodic[type].num;
        unsigned int interval, next_interval;
        dma_descr_group *groups = group_periodic[type].groups;
        dma_descr_context *next, *last;
        struct iop_usb_ttd *ttd;

        wmb(); /* ensure context is updated before changing the group list */
        while (1) {
                next = PHYS_TO_VIRT(ctxt->next);
                if (next->eol)
                        break;
                ctxt = next;
        }
        last = ctxt;

        ctxt = &ctxt_head[type];
        interval = (unsigned int) -1;
        while (1) {
                next = PHYS_TO_VIRT(ctxt->next);
                next_interval = ctxt_to_ed(next)->interval;
                if (next->eol)
                        break;
                if (next_interval != interval)
                        for (i = next_interval - 1; 
                             i < num; 
                             i += next_interval) {
                                ttd = iop_usb_ttd(&groups[i]);
                                if (ttd->mark)
                                        continue;
                                groups[i].down.context = VIRT_TO_PHYS(ctxt);
                                ttd->mark = 1;
                        }
                ctxt = next;
                interval = next_interval;
        }
        for (i = 0; i < num; i++) {
                ttd = iop_usb_ttd(&groups[i]);
                if (!ttd->mark)
                        groups[i].down.context =  VIRT_TO_PHYS(last);
                ttd->mark = 0;
        }
}

/* initialize a descriptor for an endpoint */
void iop_usb_endpoint_init(
        struct iop_usb_ed *ed, 
        enum iop_usb_transfer_type type, 
        unsigned int daddr, 
        unsigned int epnum, 
        int is_in, 
        enum iop_usb_speed speed, 
        unsigned int maxsize, 
        unsigned int interval, 
        unsigned long maxtime)
{
        struct iop_usb_ctxt_md *ctxt_md = iop_usb_ctxt_md(&ed->ctxt);

        BUG_ON((unsigned long) ed % ALIGN_IOP_USB_ED != 0);

        switch (type) {
        case IOP_USB_ISOC:
                if (interval > MAX_INTERVAL_ISOC)
                        interval = MAX_INTERVAL_ISOC;
                break;
        case IOP_USB_INTR:
                if (interval > MAX_INTERVAL_INTR)
                        interval = MAX_INTERVAL_INTR;
                break;
        case IOP_USB_CTRL:
        case IOP_USB_BULK:
                interval = 1;
                break;
        default:
                BUG();
        }

        memset(&ed->ctxt, 0, sizeof(dma_descr_context));
        ctxt_md->daddr =        daddr;
        ctxt_md->epnum =        epnum;
        ctxt_md->low_speed =    speed == IOP_USB_SPEED_LOW;
        ctxt_md->maxsize =      maxsize;
        /* Convert time from us to bit times and add marginal for
         * EOF1.  Note that the host controller delay should already
         * be included in the time passed to this function. */
        ctxt_md->maxtime =      maxtime / (1000/12) + 1 + EOF1_EARLY;
        ctxt_md->stat =         IOP_USB_STAT_OK;
        ctxt_md->toggle =       0;
        ed->ctxt.en =           1;
        ed->ctxt.dis =          1;
        ed->ctxt.store_mode =   1;
        ed->type =              type;
        ed->is_in =             is_in;
        ed->interval =          interval;
        ed->head_out =          NULL;

        if (type == IOP_USB_CTRL || is_in) {
                memset(&ed->in_group, 0, sizeof(dma_descr_group));
                ed->in_group.eol =      1;
                ed->in_group.tol =      1;
                ed->in_group.bol =      1;
                ed->in_group.down.context = VIRT_TO_PHYS(ctxt_in_eol);
                ctxt_md->in_group =     (unsigned) VIRT_TO_PHYS(&ed->in_group);
                ed->head_in =           NULL;
        }
}

/* initialize and add a descriptor for an endpoint */
void iop_usb_endpoint_add(struct iop_usb_ed *ed)
{
        unsigned int type = ed->type; 
        unsigned int interval = ed->interval;
        unsigned int next_interval;
        dma_descr_context *prev, *next;

        D(printf("add endpoint %p\n", ed));

        /* the list of context descriptors is kept sorted on interval */
        prev = &ctxt_head[type];
        while (1) {
                next = PHYS_TO_VIRT(prev->next);
                next_interval = ctxt_to_ed(next)->interval;
                if (next->eol || interval > next_interval)
                        break;
                prev = next;
        }
        /* insert in list */
        ed->ctxt.next = prev->next;
        prev->next = VIRT_TO_PHYS(&ed->ctxt);

        /* adjust group descriptor down pointers for periodic traffic */
        if (iop_usb_ttd(&group_head[type])->is_periodic)
                schedule_periodic(type, prev);
}

/* release a descriptor for an endpoint */
void iop_usb_endpoint_release(struct iop_usb_ed *ed)
{
        unsigned int type = ed->type; 
        dma_descr_context *head, *prev, *next;

        D(printf("release endpoint %p\n", ed));

        /* unlink context descriptor from list */
        prev = head = &ctxt_head[type];
        while (1) {
                next = PHYS_TO_VIRT(prev->next);
                if (next == &ed->ctxt)
                        break;
                if (next->eol)
                        return;
                prev = next;
        } 
        prev->next = ed->ctxt.next;
        ed->ctxt.en = 0;

        /* adjust group descriptor down pointers for periodic traffic */
        if (iop_usb_ttd(&group_head[type])->is_periodic)
                schedule_periodic(type, prev);
}

/* wait until a released descriptor for an endpoint is no longer used
 * by the DMA */
void iop_usb_endpoint_release_wait(struct iop_usb_ed *ed)
{

        /* busy-wait until the DMA is clear of this context to ensure
         * that the descriptor is not freed while it is still in
         * use */
        wait_on_ctxt(ed);
}

/* initialize descriptors for an USB transaction */
void iop_usb_trans_init(
        struct iop_usb_td *td,
        enum iop_usb_transaction_type type,
        unsigned int maxsize,
        void *buffer, 
        unsigned int buffer_length,
        int zeropacket)
{
        char *buf, *after;

        D(printf("trans init %p (buffer=%p)\n", td, buffer));
        
        BUG_ON(!buffer && buffer_length > 0);
        BUG_ON((unsigned long) td % ALIGN_IOP_USB_TD != 0);

        memset(td, 0, type == IOP_USB_IN ? 
               sizeof(struct iop_usb_td) : sizeof(dma_descr_data));

        td->u.priv.d_out.wait = 1;
        td->u.priv.d_out.out_eop = 1;
        iop_usb_data_md(&td->u.priv.d_out)->type = type;

        buf = buffer ? VIRT_TO_PHYS(buffer) : dummy_buf;
        after = buf + buffer_length;

        switch (type) {
        case IOP_USB_IN:
                D(printf("IN d_in=%p c_in=%p dummy=%p dummy_buf=%p\n", 
                         &td->u.priv.d_in, &td->u.priv.c_in, &td->u.priv.dummy, 
                         dummy_buf));
                td->u.priv.d_out.after = 
                        td->u.priv.d_out.buf = dummy_buf;
                /* input descriptors refers to buffer */
                td->u.priv.d_in.buf = buf;
                td->u.priv.d_in.after = after;
                td->u.priv.c_in.en = 1;
                td->u.priv.c_in.store_mode = 1;
                td->u.priv.c_in.saved_data = &td->u.priv.d_in;
                td->u.priv.c_in.saved_data_buf = buf;
                /* the number of expected packets is stored in the in
                 * context meta data */
                td->u.priv.c_in.md1 = buffer_length == 0 ? 
                        1 : (buffer_length - 1) / maxsize + 1;
                /* add dummy descriptor to catch additional data,
                 * otherwise the DMA channel will hang if the device
                 * returns more data than the driver expected */
                td->u.priv.d_in.next = VIRT_TO_PHYS(&td->u.priv.dummy);
                td->u.priv.dummy.eol = 1;
                td->u.priv.dummy.buf = dummy_buf;
                td->u.priv.dummy.after = 
                        td->u.priv.dummy.buf + DUMMY_BUF_SIZE;
                flush_dma_list(&td->u.priv.d_in);
                break;
        case IOP_USB_OUT:
                D(printf("OUT/SETUP\n")); 
                if (zeropacket && (buffer_length % maxsize == 0))
                        iop_usb_data_md(&td->u.priv.d_out)->zend = 1;
                /*FALLTHROUGH*/
        case IOP_USB_SETUP:
                td->u.priv.d_out.buf = buf;
                td->u.priv.d_out.after = after;
                break;
        }
}

/* insert descriptors in output list */
static int insert_descr_out(struct iop_usb_ed *ed, struct iop_usb_td *td)
{
        struct iop_usb_td *last = td;

        /* find end of the new descriptors and set EOL, convert next
         * pointers to physical addresses at the same time */
        while (last->u.next) {
                struct iop_usb_td *next = last->u.next;
                last->u.next = VIRT_TO_PHYS(next);
                last = next;
        }
        last->u.priv.d_out.eol = 1; /* terminate list */
        wmb();
        if (ed->head_out) {
                /* insert at end of existing list */
                struct iop_usb_td *prev;
                for (prev = ed->head_out; 
                     !prev->u.priv.d_out.eol; 
                     prev = PHYS_TO_VIRT(prev->u.next))
                        ;
                prev->u.next = VIRT_TO_PHYS(td);
                prev->u.priv.d_out.eol = 0;
        } else {
                /* list is empty */
                ed->head_out = td;
                reset_out_context(ed, td);
        }
        if (ed->ctxt.dis) {
                /* check if endpoint has halted */
                if (iop_usb_ctxt_md(&ed->ctxt)->stat != IOP_USB_STAT_OK)
                        return -1;
                if (ed->ctxt.saved_data == VIRT_TO_PHYS(&last->u.priv.d_out))
                        return 0;
                /* DMA stopped before processing the new data descriptor */
                reset_out_context(ed, td);
        }
        return 0;
}

/* insert descriptors in input list */
static void insert_descr_in(struct iop_usb_ed *ed, struct iop_usb_td *td)
{
        dma_descr_context *first = NULL, *prev = NULL, *cur = NULL;

        if (ed->type != IOP_USB_CTRL && !ed->is_in)
                return;

        /* assemble list of input context descriptors */
        for (; td; td = td->u.next)
                if (iop_usb_data_md(&td->u.priv.d_out)->type == IOP_USB_IN) {
                        cur = &td->u.priv.c_in;
                        if (!first)
                                first = cur;
                        if (prev) 
                                prev->next = VIRT_TO_PHYS(cur);
                        prev = cur;
                }
        if (!first)
                return; /* no input descriptors */

        cur->next = VIRT_TO_PHYS(ctxt_in_eol); /* terminate list */
        if (ed->head_in) {
                /* insert at end of existing list */
                prev = NULL;
                cur = ed->head_in;
                do {
                        prev = cur;
                        cur = PHYS_TO_VIRT(cur->next);
                } while (!cur->eol);
                prev->next = VIRT_TO_PHYS(first);
        } else {
                /* list is empty */
                ed->head_in = first;
        }
        /* reset context pointer in in_group if it has reached end of list */
        if (ed->in_group.down.context == VIRT_TO_PHYS(ctxt_in_eol))
                ed->in_group.down.context = VIRT_TO_PHYS(first);
}

/* remove descriptors from output list */
static void remove_descr_out(
        struct iop_usb_ed *ed,
        struct iop_usb_td *first,
        struct iop_usb_td *last)
{
        struct iop_usb_td *after, *cur;
        dma_descr_data *saved_data = PHYS_TO_VIRT(ed->ctxt.saved_data);

        BUG_ON(ed->ctxt.en);

        after = last->u.priv.d_out.eol ? NULL : PHYS_TO_VIRT(last->u.next);

        if (ed->head_out == first) {
                /* descriptors to remove is at the head of the list */
                ed->head_out = after;
        } else {
                /* search the list for the first descriptor to remove */
                struct iop_usb_td *prev;
                for (prev = ed->head_out;
                     !prev->u.priv.d_out.eol;
                     prev = PHYS_TO_VIRT(prev->u.next))
                        if (PHYS_TO_VIRT(prev->u.next) == first)
                                break;
                BUG_ON(prev->u.priv.d_out.eol); /* first not found */
                if (!after)
                        prev->u.priv.d_out.eol = 1;
                prev->u.next = after;
        }
        /* reset context if current descriptor is removed, convert
         * next pointers back to virtual addresses at the same time */ 
        for (cur = first; ; cur = cur->u.next) {
                if (&cur->u.priv.d_out == saved_data)
                        reset_out_context(ed, after);
                cur->u.next = PHYS_TO_VIRT(cur->u.next);
                if (cur == last || cur->u.priv.d_out.eol)
                        break;
        }
        BUG_ON(cur != last); /* last not found */
        last->u.next = NULL;
}
        
/* remove descriptors from input list */
static void remove_descr_in(
        struct iop_usb_ed *ed,
        struct iop_usb_td *first,
        struct iop_usb_td *last)
{
        struct iop_usb_td *td;
        dma_descr_context *first_in, *last_in, *after, *cur;
        dma_descr_context *down = PHYS_TO_VIRT(ed->in_group.down.context);

        BUG_ON(ed->ctxt.en && !ed->ctxt.dis);

        if (ed->type != IOP_USB_CTRL && !ed->is_in)
                return;

        /* find input context descriptors to remove */
        first_in = last_in = NULL;
        for (td = first; ; td = PHYS_TO_VIRT(td->u.next)) {
                if (iop_usb_data_md(&td->u.priv.d_out)->type == IOP_USB_IN) {
                        last_in = &td->u.priv.c_in;
                        if (!first_in)
                                first_in = last_in;
                }
                if (td == last)
                        break;
                BUG_ON(td->u.priv.d_out.eol);
        }
        if (!first_in)
                return; /* no IN transactions to remove */

        /* note that the list is terminated with ctxt_in_eol
         * descriptors, but an empty list is represented by NULL */
        after = PHYS_TO_VIRT(last_in->next);
        /* handle case were the descriptors to remove is at the head
         * of the list */
        if (ed->head_in == first_in) {
                /* descriptors to remove is at the head of the list */
                ed->head_in = after->eol ? NULL :  after;
        } else {
                /* search the list for the first descriptor to remove */
                dma_descr_context *prev;
                for (prev = ed->head_in;
                     !prev->eol;
                     prev = PHYS_TO_VIRT(prev->next))
                        if (PHYS_TO_VIRT(prev->next) == first_in)
                                break;
                BUG_ON(prev->eol); /* first not found */
                prev->next = after;
        }
        /* reset group if current descriptor is removed */
        for (cur = first_in; !cur->eol; cur = PHYS_TO_VIRT(cur->next)) {
                if (cur == down)
                        ed->in_group.down.context = VIRT_TO_PHYS(after);
                if (cur == last_in)
                        break;
        }
        BUG_ON(cur != last_in); /* last not found */
        last_in->next = NULL;
}

/* enqueue DMA descriptors for an USB transaction */
int iop_usb_trans_enqueue(struct iop_usb_ed *ed, struct iop_usb_td *td)
{
        int retval = 0;

        D(printf("trans enqueue %p -> %p\n", td, ed));

        insert_descr_in(ed, td);
        wmb();
        retval = insert_descr_out(ed, td);
        if (retval != 0) {
                /* note that in this case the context will have been
                 * disabled by the MPU so it is safe to remove the in
                 * descriptor */
                remove_descr_in(ed, td, td);
                return IOP_USB_ERR_CTXT_DIS;
        }
        enable_group(ed->type);
        return IOP_USB_OK;
}

/* lock an endpoint to allow dequeuing data descriptors for an USB
 * transaction */
void iop_usb_trans_dequeue_lock(struct iop_usb_ed *ed)
{
        /* disable the context to ensure that the dequeuing is atomic
         * from the DMA point of view */
        ed->ctxt.en = 0;
        /* busy-wait while the DMA is working on the context */
        wait_on_ctxt(ed);
}

/* dequeue data descriptors for an USB transaction */
int iop_usb_trans_dequeue(struct iop_usb_ed *ed,
                          struct iop_usb_td *td_first,
                          struct iop_usb_td *td_last)
{
        D(printf("trans dequeue %p:%p -> %p\n", td_first, td_last, ed));

        BUG_ON(ed->ctxt.en);

        if (iop_usb_data_md(&td_last->u.priv.d_out)->done)
                return IOP_USB_ERR_ALL_DONE;

        remove_descr_in(ed, td_first, td_last);
        wmb();
        remove_descr_out(ed, td_first, td_last);
        wmb();
        return IOP_USB_OK;
}

/* unlock an endpoint after dequeueing data descriptors for an USB
   transaction */
void iop_usb_trans_dequeue_unlock(struct iop_usb_ed *ed)
{
        BUG_ON(ed->ctxt.en);

        if (ed->ctxt.saved_data) {
                if (ed->type == IOP_USB_CTRL || ed->type == IOP_USB_BULK) {
                        static int fe_irq_request(void);
                        /* DMA may disable the the group if no other
                         * contexts are enabled */
                        enable_group(ed->type);
                        /* It is still possible that the DMA disables
                         * the group after the enabling above. Request
                         * an interrupt at the end of the current
                         * frame and let finish_data() take care of
                         * this case. */
                        fe_irq_request();
                }
        } else
                ed->ctxt.dis = 1;
        wmb();
        ed->ctxt.en = 1;
}

/* stop processing peridic traffic of the specified type until more
 * traffic is submitted */
void iop_usb_stop_periodic(enum iop_usb_transfer_type type)
{
        BUG_ON(type != IOP_USB_ISOC && type != IOP_USB_INTR);
        group_head[type].en = 0;
}

/* return completed data descriptors to upper layer */
static void finish_data(
        struct iop_usb_ed *ed, 
        void (*cb)(struct iop_usb_td *, int, int))
{
        struct iop_usb_td *next, *td = ed->head_out;
        struct iop_usb_data_md *data_md;
        dma_descr_data *data = &td->u.priv.d_out;
        dma_descr_context *ctxt_in;
        unsigned int ep_stat;

        if (!td)
                return; /* nothing to do */
        ctxt_in = (ed->type == IOP_USB_CTRL || ed->is_in) ? ed->head_in : NULL;
        /* if the EP has stopped on an error all pending data should
         * be flushed, return it with status set to no error and
         * length set to zero */
        ep_stat = iop_usb_ctxt_md(&ed->ctxt)->stat;
        rmb();
        while ((data_md = iop_usb_data_md(data))->done || 
               ep_stat != IOP_USB_STAT_OK) {
                int length = 0;
                int status = 
                        data_md->done ? data_md->stat : IOP_USB_STAT_FLUSHED;
                /* get length from descriptor */
                switch (data_md->type) {
                case IOP_USB_IN:
                        /* first verify that the output and input
                         * lists are in sync */
                        BUG_ON(!ctxt_in || ctxt_in->eol);
                        BUG_ON(ctxt_in != &td->u.priv.c_in);
                        if (status != IOP_USB_STAT_FLUSHED) {
                                dma_descr_data *data_in = &td->u.priv.d_in;
                                length = data_in->after - data_in->buf;
                                /* EOP should be set in the data
                                 * descriptor, otherwise we have got
                                 * an overrun into the dummy data
                                 * descriptor */
                                if (status == IOP_USB_STAT_OK && !data_in->in_eop)
                                        status = IOP_USB_STAT_ORUN;
                        }
                        ctxt_in = PHYS_TO_VIRT(ctxt_in->next);
                        break;
                case IOP_USB_OUT:
                        if (status != IOP_USB_STAT_FLUSHED)
                                length = data->after - data->buf;
                        break;
                default:
                        break;
                }
                /* restore pointers before calling the callback */
                next = td->u.next ? PHYS_TO_VIRT(td->u.next) : NULL;
                td->u.next = next;
                wmb();
                data->buf = PHYS_TO_VIRT(data->buf);
                data->after = PHYS_TO_VIRT(data->after);
                cb((struct iop_usb_td *) td, status, length);
                if (data->eol) {
                        td = NULL;
                        break;
                }
                td = next;
                data = &td->u.priv.d_out;
        }
        /* clear error condition, if any */
        if (ep_stat != IOP_USB_STAT_OK) {
                BUG_ON(!ed->ctxt.dis);
                reset_ed_status(ed);
        }
        ed->head_out = (struct iop_usb_td *) td;
        if (ed->type == IOP_USB_CTRL || ed->is_in)
                ed->head_in = (dma_descr_context *) ctxt_in;
        if (!ed->head_out) {
                /* have processed all data */
                ed->ctxt.dis = 1;
                if (ed->type == IOP_USB_CTRL || ed->is_in) {
                        BUG_ON(ed->head_in && !ed->head_in->eol);
                        ed->head_in = NULL;
                        ed->in_group.down.context = VIRT_TO_PHYS(ctxt_in_eol);
                }
                return;
        }
        /* handle race condition where the DMA disabled the context
         * while we were inserting data into the list */
        if (ed->ctxt.dis)
                reset_out_context(ed, ed->head_out);
        /* also handle case where the DMA disabled the group */
        if (ed->type == IOP_USB_CTRL || ed->type == IOP_USB_BULK)
                enable_group(ed->type);
}

/* interrupt handler for IOP_USB_IRQ_TRANS_DONE */
void iop_usb_trans_done_irq(void (*cb)(struct iop_usb_td *, int, int))
{
        unsigned int type;

        /* check all endpoints for completed data descriptors */
        for (type = 0; type < NUM_TRANSFER_TYPE; type++) {
                dma_descr_context *ctxt = &ctxt_head[type];
                while (1) {
                        ctxt = PHYS_TO_VIRT(ctxt->next);
                        if (ctxt->eol)
                                break;
                        finish_data(ctxt_to_ed(ctxt), cb);
                }
        }
}

/* wait for the MPU instruction register to become idle, with timeout */
static __inline__ int wait_mpu_idle(void)
{
        reg_iop_mpu_r_stat mpu_stat;
        unsigned int timeout = IOP_TIMEOUT;

        do {
                mpu_stat = REG_RD(iop_mpu, regi_iop_mpu, r_stat);
        } while (mpu_stat.instr_reg_busy == regk_iop_mpu_yes && --timeout > 0);
        return timeout > 0 ? 0 : -1;
}

/* wait for the MPU_REG_DATA register to become zero, with timeout */
static __inline__ int wait_mpu_reg_data(void)
{
        int data;
        unsigned int timeout = IOP_TIMEOUT;

        do {
                data = REG_RD_VECT(iop_mpu, regi_iop_mpu, rw_r, MPU_REG_DATA);
        } while (data && --timeout > 0);
        return timeout > 0 ? 0 : -1;
}

/* read MPU memory */
static int read_mpu_mem(u32 addr, u32 *data)
{
        reg_iop_mpu_rw_ctrl ctrl = REG_RD(iop_mpu, regi_iop_mpu, rw_ctrl);
        
        if (wait_mpu_idle() != 0)
                return -1;
        if (ctrl.en) {
                REG_WR_VECT(iop_mpu, regi_iop_mpu, rw_r, MPU_REG_DATA, addr);
                REG_WR(iop_mpu, regi_iop_mpu, rw_instr, 
                       MPU_JIR_I(MK_DWORD_ADDR(MPU_ADDR_READ_MEM)));
        } else 
                REG_WR(iop_mpu, regi_iop_mpu, rw_instr, 
                       MPU_LW_IR(MK_DWORD_ADDR(addr), MPU_REG_DATA));
        if (wait_mpu_idle() != 0)
                return -1;
        *data = REG_RD_VECT(iop_mpu, regi_iop_mpu, rw_r, MPU_REG_DATA);
        return 0;
}

/* write MPU memory */
static int write_mpu_mem(u32 addr, u32 data)
{
        if (wait_mpu_idle() != 0)
                return -1;
        REG_WR_VECT(iop_mpu, regi_iop_mpu, rw_r, MPU_REG_DATA, data);
        REG_WR(iop_mpu, regi_iop_mpu, rw_instr, 
               MPU_SW_RI(MPU_REG_DATA, MK_DWORD_ADDR(addr)));
        if (wait_mpu_idle() != 0)
                return -1;
        return 0;
}

/* halt the MPU */
static int mpu_halt(void)
{
        if (wait_mpu_idle() != 0)
                return -1;
        REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_HALT());
        if (wait_mpu_idle() != 0)
                return -1;
        return 0;
}

/* start the MPU */
static int mpu_start(void)
{
        reg_iop_mpu_rw_ctrl mpu_ctrl = { .en = regk_iop_mpu_yes };

        /* reset MPU PC and wait for it to bite */
        if (wait_mpu_idle() != 0)
                return IOP_USB_ERR_TIMEOUT;
        REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_BA_I(MPU_ADDR_START));
        if (wait_mpu_idle() != 0)
                return IOP_USB_ERR_TIMEOUT;

        /* make sure the MPU starts executing with interrupts disabled */
        REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_DI());
        if (wait_mpu_idle() != 0)
                return -1;

        /* ok, lets go! */
        REG_WR(iop_mpu, regi_iop_mpu, rw_ctrl, mpu_ctrl);

        return 0;
}

/* call interrupt routine in MPU to set flags to initiate a set or
 * clear feature request to the root hub */
static int mpu_rh_port_request(
        unsigned int req, 
        unsigned int port, 
        unsigned int feat)
{
        static u32 addr = 0;
        u32 data = CPU_DATA_VAL(req, port, feat);

        if (!addr && read_mpu_mem(MPU_ADDR_RH_PORT_REQ, &addr) != 0)
                return -1;
        if (wait_mpu_idle() != 0)
                return -1;
        REG_WR_VECT(iop_mpu, regi_iop_mpu, rw_r, MPU_REG_DATA, data);
        REG_WR(iop_mpu, regi_iop_mpu, rw_instr, 
               MPU_JIR_I(MK_DWORD_ADDR(addr)));
        if (wait_mpu_reg_data() != 0)
                return -1;
        return 0;
}

/* call interrupt routine in MPU to set flag to request an interrupt
 * at the end of the current frame */
static int fe_irq_request(void)
{
        static u32 addr = 0;

        if (!addr && read_mpu_mem(MPU_ADDR_FE_IRQ_REQ, &addr) != 0)
                return -1;
        if (wait_mpu_idle() != 0)
                return -1;
        REG_WR(iop_mpu, regi_iop_mpu, rw_instr, 
               MPU_JIR_I(MK_DWORD_ADDR(addr)));
        return 0;
}

/* configure GIO for a port */
static void port_gio_config(unsigned int port, int low_speed)
{
        reg_iop_sw_cfg_rw_gio_out_grp0_cfg cfg0;
        reg_iop_sw_cfg_rw_gio_out_grp1_cfg cfg1;
        reg_iop_sw_cfg_rw_gio_out_grp2_cfg cfg2;
        reg_iop_sw_cfg_rw_gio_out_grp3_cfg cfg3;
        reg_iop_sw_cfg_rw_gio_out_grp4_cfg cfg4;
        reg_iop_sw_cfg_rw_gio_out_grp5_cfg cfg5;
        reg_iop_sw_cfg_rw_gio_out_grp6_cfg cfg6;
        reg_iop_sw_cfg_rw_gio_out_grp7_cfg cfg7;
        reg_iop_sap_in_rw_gio sap_in;
        reg_iop_sw_cpu_rw_gio_set_mask set_mask;
        reg_iop_sw_cpu_rw_gio_clr_mask clr_mask;
        unsigned int spu_v_mo, spu_v_po, spu_oe;
        unsigned int gio_speed, gio_rcv = GIO_RCV;

        /* map V_PO/V_MO and OE from SPU to GIO_OUT */
        switch (INST(spu)) {
        case regi_iop_spu0:
                spu_v_mo =  regk_iop_sw_cfg_spu0_gioout0;
                spu_v_po =  regk_iop_sw_cfg_spu0_gioout2;
                spu_oe =    regk_iop_sw_cfg_spu0_gioout16;
                break;
        case regi_iop_spu1:
                spu_v_mo =  regk_iop_sw_cfg_spu1_gioout0;
                spu_v_po =  regk_iop_sw_cfg_spu1_gioout2;
                spu_oe =    regk_iop_sw_cfg_spu1_gioout16;
                break;
        default:
                BUG();
        }
        if (low_speed) {
                /* swap v_po and v_mo for low speed signaling */
                unsigned int tmp = spu_v_mo;
                spu_v_mo = spu_v_po;
                spu_v_po = tmp;
        }
        switch (port) {
        case 0:
                cfg2 = REG_RD(iop_sw_cfg, regi_iop_sw_cfg, rw_gio_out_grp2_cfg);
                cfg6 = REG_RD(iop_sw_cfg, regi_iop_sw_cfg, rw_gio_out_grp6_cfg);
                cfg2.gio8 =  spu_v_mo;
                cfg2.gio9 =  spu_v_po;
                cfg6.gio24 = spu_oe;
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_gio_out_grp2_cfg, cfg2);
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_gio_out_grp6_cfg, cfg6);
                gio_speed = PORT_GIO_SPEED(0);
                gio_rcv += GIO_PORT_BASE(0);
                break;
        case 1:
                cfg3 = REG_RD(iop_sw_cfg, regi_iop_sw_cfg, rw_gio_out_grp3_cfg);
                cfg7 = REG_RD(iop_sw_cfg, regi_iop_sw_cfg, rw_gio_out_grp7_cfg);
                cfg3.gio12 = spu_v_mo;
                cfg3.gio13 = spu_v_po;
                cfg7.gio28 = spu_oe;
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_gio_out_grp3_cfg, cfg3);
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_gio_out_grp7_cfg, cfg7);
                gio_speed = PORT_GIO_SPEED(1);
                gio_rcv += GIO_PORT_BASE(1);
                break;
        case 2: 
                cfg1 = REG_RD(iop_sw_cfg, regi_iop_sw_cfg, rw_gio_out_grp1_cfg);
                cfg5 = REG_RD(iop_sw_cfg, regi_iop_sw_cfg, rw_gio_out_grp5_cfg);
                cfg1.gio4 =  spu_v_mo;
                cfg1.gio5 =  spu_v_po;
                cfg5.gio20 = spu_oe;
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_gio_out_grp1_cfg, cfg1);
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_gio_out_grp5_cfg, cfg5);
                gio_speed = PORT_GIO_SPEED(2);
                gio_rcv += GIO_PORT_BASE(2);
                break;
        case 3:
                cfg0 = REG_RD(iop_sw_cfg, regi_iop_sw_cfg, rw_gio_out_grp0_cfg);
                cfg4 = REG_RD(iop_sw_cfg, regi_iop_sw_cfg, rw_gio_out_grp4_cfg);
                cfg0.gio0 =  spu_v_mo;
                cfg0.gio1 =  spu_v_po;
                cfg4.gio16 = spu_oe;
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_gio_out_grp0_cfg, cfg0);
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_gio_out_grp4_cfg, cfg4);
                gio_speed = PORT_GIO_SPEED(3);
                gio_rcv += GIO_PORT_BASE(3);
                break;
        default:
                BUG();
        }
        /* set logic for GIO_IN depending on speed */
        sap_in = REG_RD_VECT(iop_sap_in, regi_iop_sap_in, rw_gio, gio_rcv);
        sap_in.logic = low_speed ? regk_iop_sap_in_inv : regk_iop_sap_in_none;
        REG_WR_VECT(iop_sap_in, regi_iop_sap_in, rw_gio, gio_rcv, sap_in);
        /* set SPEED using set/clr masks */
        set_mask = REG_RD(iop_sw_cpu, regi_iop_sw_cpu, rw_gio_set_mask);
        clr_mask = REG_RD(iop_sw_cpu, regi_iop_sw_cpu, rw_gio_clr_mask);
        if (!low_speed) {
                set_mask.val |=  gio_speed;
                clr_mask.val &= ~gio_speed;
        } else {
                set_mask.val &= ~gio_speed;
                clr_mask.val |=  gio_speed;
        }
        REG_WR(iop_sw_cpu, regi_iop_sw_cpu, rw_gio_set_mask, set_mask);
        REG_WR(iop_sw_cpu, regi_iop_sw_cpu, rw_gio_clr_mask, clr_mask);
}

/* initialize multiplexing of DMA channels and pins, start clock */
int __init_or_module iop_usb_init(
        unsigned int dma_map, 
        unsigned int ports, 
        int int_phy)
{
        /* store configuration */
        iop_usb_cfg.dma_map = dma_map;
        iop_usb_cfg.ports = ports;
        iop_usb_cfg.int_phy = int_phy;

        if (ports == 0 || (ports & 0xf) == 0)
                return IOP_USB_ERR_INVAL;
        if (dma_map > 1)
                return IOP_USB_ERR_INVAL;
        if (alloc_dummy_buf() != 0 || alloc_static_descrs() != 0)
                return IOP_USB_ERR_BUSY;

        /* DMA channels */
        if (iop_request_dma(dma_map, INST(dma_in), "crisv32_hcd") != 0)
                goto out_0;
        if (iop_request_dma(dma_map, INST(dma_out), "crisv32_hcd") != 0)
                goto out_1;

        /* pinmux */
        if (port_in_use(0) && int_phy != 0)
                if (iop_pinmux_alloc(PORT_C, 8, 14) != 0)
                        goto out_2;
        if (port_in_use(1) && int_phy != 1)
                if (iop_pinmux_alloc(PORT_E, 8, 14) != 0)
                        goto out_3;
        if (port_in_use(2))
                if (iop_pinmux_alloc(PORT_D, 8, 14) != 0)
                        goto out_4;
        if (port_in_use(3))
                if (iop_pinmux_alloc(PORT_B, 8, 14) != 0)
                        goto out_5;
        iop_usb_phy(int_phy);

        iop_start_clock();

        return IOP_USB_OK;

 out_5:
        if (port_in_use(2))
                iop_pinmux_dealloc(PORT_D, 8, 14);
 out_4:
        if (port_in_use(1) && int_phy != 1)
                iop_pinmux_dealloc(PORT_E, 8, 14); 
 out_3:
        if (port_in_use(0) && int_phy != 0)
                iop_pinmux_dealloc(PORT_C, 8, 14);
 out_2:
        iop_free_dma(INST(dma_out));
 out_1:
        iop_free_dma(INST(dma_in));
 out_0:
        return IOP_USB_ERR_BUSY;
}

/* free resources allocated by iop_usb_init() */
void iop_usb_exit(void)
{
        int intr0_mask;

        intr0_mask = REG_RD_INT(iop_sw_cpu, regi_iop_sw_cpu, rw_intr0_mask);
        intr0_mask &= ~CPU_IRQ_MASK;
        REG_WR_INT(iop_sw_cpu, regi_iop_sw_cpu, rw_intr0_mask, intr0_mask);

        iop_free_dma(INST(dma_in));
        iop_free_dma(INST(dma_out));
        iop_pinmux_dealloc(PORT_C, 8, 14);
        iop_pinmux_dealloc(PORT_E, 8, 14); 
        iop_pinmux_dealloc(PORT_D, 8, 14);
        iop_pinmux_dealloc(PORT_B, 8, 14);
}

/* configure IOP */
void __init_or_module iop_usb_config(void)
{
        reg_iop_sw_cfg_rw_pdp0_cfg pdp0_cfg;
        reg_iop_sw_cfg_rw_pdp1_cfg pdp1_cfg;
        reg_iop_dmc_in_rw_cfg dmc_in_cfg = {
                .last_dis_dif =         regk_iop_dmc_in_no,
                .sth_intr =             regk_iop_dmc_in_lim64,
        };
        reg_iop_dmc_in_rw_ctrl dmc_in_ctrl = {
                .stream_clr =           regk_iop_dmc_in_no,
                .dif_dis =              regk_iop_dmc_in_no,
                .dif_en =               regk_iop_dmc_in_yes,
        };
        reg_iop_dmc_in_rw_stream_ctrl dmc_in_stream_ctrl = {
                .size =                 0,
                .keep_md =              regk_iop_dmc_in_yes,
                .wait =                 regk_iop_dmc_in_yes,
                .eop =                  regk_iop_dmc_in_no,
        };
        reg_iop_fifo_in_rw_cfg fifo_in_cfg = {
                .mode =                 regk_iop_fifo_in_size8,
                .last_dis_dif_in =      regk_iop_fifo_in_no,
                .trig =                 regk_iop_fifo_in_pos,
                .byte_order =           regk_iop_fifo_in_order8,
                .avail_lim =            3,
        };
        reg_iop_fifo_in_rw_ctrl fifo_in_ctrl = {
                .dif_out_en =           regk_iop_fifo_in_yes,
                .dif_in_en =            regk_iop_fifo_in_yes,
        };
        reg_iop_fifo_out_rw_ctrl fifo_out_ctrl = {
                .dif_out_en =           regk_iop_fifo_out_no,
                .dif_in_en =            regk_iop_fifo_out_yes,
        };
        reg_iop_fifo_out_rw_cfg fifo_out_cfg = {
                .mode =                 regk_iop_fifo_out_size8,
                .last_dis_dif_out =     regk_iop_fifo_out_no,
                .last_dis_dif_in =      regk_iop_fifo_out_no,
                .byte_order =           regk_iop_fifo_out_order8,
                .free_lim =             4,
        };
        reg_iop_scrc_out_rw_cfg scrc_out_cfg = {
                .inv_crc =              regk_iop_scrc_out_yes,
        };
        reg_iop_crc_par_rw_cfg crc_par_cfg = {
                .poly =                 regk_iop_crc_par_crc16,
                .crc_out =              regk_iop_crc_par_no,
                .mode =                 regk_iop_crc_par_check,
        };
        unsigned int mask;
        reg_iop_sw_cfg_rw_gio_mask gio_mask;
        reg_iop_sw_cfg_rw_gio_oe_mask gio_oe_mask;
        reg_iop_sw_cpu_rw_gio_oe_set_mask gio_oe_set_mask;
        reg_iop_sap_in_rw_gio sap_in0 = {
                .logic =                regk_iop_sap_in_none,
                .sync_sel =             regk_iop_sap_in_two_clk200,
        };
        reg_iop_sap_in_rw_gio sap_in1 = {
                .logic =                regk_iop_sap_in_or,
                .sync_sel =             regk_iop_sap_in_two_clk200,
        };
        reg_iop_sap_out_rw_gio sap_out = {
                .oe_logic =             regk_iop_sap_out_none,
                .oe_clk_sel =           regk_iop_sap_out_none,
                .out_logic =            regk_iop_sap_out_none,
                .out_clk_inv =          regk_iop_sap_out_no,
                .out_clk_sel =          regk_iop_sap_out_clk12,
        };
        reg_iop_timer_grp_rw_cfg tmr_grp_cfg = {
                .clk_src =              regk_iop_timer_grp_ext,
                .trig =                 regk_iop_timer_grp_pos_neg,
        };
        reg_iop_timer_grp_rw_half_period half_period = {
                .quota_hi_sel =         regk_iop_timer_grp_short_period,
                .quota_hi =             1,
                .quota_lo =             0,
        };
        reg_iop_timer_grp_rw_tmr_cfg sof_tmr_cfg = {
                .rst_at_en_strb =       regk_iop_timer_grp_no,
                .dis_only_by_reg =      regk_iop_timer_grp_yes,
                .en_only_by_reg  =      regk_iop_timer_grp_yes,
                .inv =                  regk_iop_timer_grp_no,
                .active_on_tmr =        SOF_TMR,
                .out_mode =             regk_iop_timer_grp_pulse,
                .run_mode =             regk_iop_timer_grp_stop,
                .strb =                 regk_iop_timer_grp_pos,
                .clk_src =              regk_iop_timer_grp_clk_gen,
        };
        reg_iop_timer_grp_rw_tmr_cfg eof2_tmr_cfg = {
                .rst_at_en_strb =       regk_iop_timer_grp_yes,
                .dis_only_by_reg =      regk_iop_timer_grp_yes,
                .en_only_by_reg  =      regk_iop_timer_grp_no,
                .inv =                  regk_iop_timer_grp_no,
                .active_on_tmr =        EOF2_TMR,
                .out_mode =             regk_iop_timer_grp_toggle,
                .run_mode =             regk_iop_timer_grp_once,
                .strb =                 regk_iop_timer_grp_pos,
                .clk_src =              regk_iop_timer_grp_clk_gen,
                .en_by_tmr =            SOF_TMR,
        };
        reg_iop_timer_grp_rw_tmr_cfg rx_cnt_tmr_cfg = {
                .rst_at_en_strb =       regk_iop_timer_grp_no,
                .dis_only_by_reg =      regk_iop_timer_grp_yes,
                .en_only_by_reg  =      regk_iop_timer_grp_yes,
                .inv =                  regk_iop_timer_grp_no,
                .active_on_tmr =        RX_CNT_TMR,
                .out_mode =             regk_iop_timer_grp_pulse,
                .run_mode =             regk_iop_timer_grp_once,
                .strb =                 regk_iop_timer_grp_pos,
                .clk_src =              regk_iop_timer_grp_clk_gen,
        };
        reg_iop_timer_grp_rw_tmr_len sof_tmr_len = {
                .val =                  FRAME_TIME - 1
        };
        reg_iop_timer_grp_rw_tmr_len eof2_tmr_len = {
                .val =                  FRAME_TIME - EOF2_NOM - 1
        };
        reg_iop_timer_grp_rw_cmd tmr_grp_cmd_rst = { 
                .rst =                  1<<SOF_TMR | 1<<EOF2_TMR
        };
        reg_iop_timer_grp_rw_cmd tmr_grp_cmd_en = { 
                .en =                   1<<SOF_TMR | 1<<EOF2_TMR
        };
        reg_iop_sw_cfg_rw_timer_grp0_cfg tmr_grp0_cfg;
        reg_iop_sw_cfg_rw_timer_grp1_cfg tmr_grp1_cfg;
        reg_iop_sw_cfg_rw_timer_grp2_cfg tmr_grp2_cfg;
        reg_iop_sw_cfg_rw_timer_grp3_cfg tmr_grp3_cfg;
        reg_iop_sw_cfg_rw_spu0_owner spu0_owner = {
                .cfg =                  regk_iop_sw_cfg_mpu
        };
        reg_iop_sw_cfg_rw_spu1_owner spu1_owner = {
                .cfg =                  regk_iop_sw_cfg_mpu
        };
        reg_iop_sw_cfg_rw_dmc_in0_owner dmc_in0_owner = {
                .cfg =                  regk_iop_sw_cfg_mpu
        };
        reg_iop_sw_cfg_rw_dmc_in1_owner dmc_in1_owner = {
                .cfg =                  regk_iop_sw_cfg_mpu
        };
        reg_iop_sw_cfg_rw_dmc_out0_owner dmc_out0_owner = {
                .cfg =                  regk_iop_sw_cfg_mpu
        };
        reg_iop_sw_cfg_rw_dmc_out1_owner dmc_out1_owner = {
                .cfg =                  regk_iop_sw_cfg_mpu
        };
        reg_iop_sw_cfg_rw_fifo_in0_owner fifo_in0_owner = {
                .cfg =                  regk_iop_sw_cfg_mpu
        };
        reg_iop_sw_cfg_rw_fifo_in1_owner fifo_in1_owner = {
                .cfg =                  regk_iop_sw_cfg_mpu
        };
        unsigned int spu = -1;
        reg_iop_sw_cfg_rw_fifo_out0_owner fifo_out0_owner;
        reg_iop_sw_cfg_rw_fifo_out1_owner fifo_out1_owner;
        reg_iop_sw_cfg_rw_fifo_out0_extra_owner fifo_out0_extra_owner = {
                .cfg =                  regk_iop_sw_cfg_mpu

        };
        reg_iop_sw_cfg_rw_fifo_out1_extra_owner fifo_out1_extra_owner = {
                .cfg =                  regk_iop_sw_cfg_mpu
        };
        reg_iop_sw_cfg_rw_scrc_out0_owner scrc_out0_owner;
        reg_iop_sw_cfg_rw_scrc_out1_owner scrc_out1_owner;
        reg_iop_sw_cfg_rw_crc_par0_owner crc_par0_owner;
        reg_iop_sw_cfg_rw_crc_par1_owner crc_par1_owner;
        reg_iop_sw_cfg_rw_timer_grp0_owner timer_grp0_owner = {
                .cfg =                  regk_iop_sw_cfg_mpu
        };
        reg_iop_sw_cfg_rw_timer_grp1_owner timer_grp1_owner = {
                .cfg =                  regk_iop_sw_cfg_mpu
        };
        reg_iop_sw_cfg_rw_timer_grp2_owner timer_grp2_owner = {
                .cfg =                  regk_iop_sw_cfg_mpu
        };
        reg_iop_sw_cfg_rw_timer_grp3_owner timer_grp3_owner = {
                .cfg =                  regk_iop_sw_cfg_mpu
        };

        /* Parallel Data Path */
        switch (iop_usb_cfg.dma_map) {
        case 0:
                pdp0_cfg = REG_RD(iop_sw_cfg, regi_iop_sw_cfg, rw_pdp0_cfg);
                pdp0_cfg.out_src =      regk_iop_sw_cfg_dmc0;
                pdp0_cfg.dmc0_usr =     regk_iop_sw_cfg_par0;
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_pdp0_cfg, pdp0_cfg);
                break;
        case 1:
                pdp1_cfg = REG_RD(iop_sw_cfg, regi_iop_sw_cfg, rw_pdp1_cfg);
                pdp1_cfg.out_src =      regk_iop_sw_cfg_dmc1;
                pdp1_cfg.dmc1_usr =     regk_iop_sw_cfg_par1;
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_pdp1_cfg, pdp1_cfg);
                break;
        default:
                BUG();
        }

        /* DMC In */
        REG_WR(iop_dmc_in, INST(dmc_in), rw_cfg, dmc_in_cfg);
        REG_WR(iop_dmc_in, INST(dmc_in), rw_ctrl, dmc_in_ctrl);
        REG_WR(iop_dmc_in, INST(dmc_in), rw_stream_ctrl, dmc_in_stream_ctrl);

        /* FIFO In */
        REG_WR(iop_fifo_in, INST(fifo_in), rw_cfg, fifo_in_cfg);
        REG_WR(iop_fifo_in, INST(fifo_in), rw_ctrl, fifo_in_ctrl);

        /* FIFO Out */
        REG_WR(iop_fifo_out, INST(fifo_out), rw_ctrl, fifo_out_ctrl);
        REG_WR(iop_fifo_out, INST(fifo_out), rw_cfg, fifo_out_cfg);

        /* Serial CRC Out */
        REG_WR(iop_scrc_out, INST(scrc_out), rw_cfg, scrc_out_cfg);

        /* Parallel CRC */
        REG_WR(iop_crc_par, INST(crc_par), rw_cfg, crc_par_cfg);
        REG_WR(iop_crc_par, INST(crc_par), rw_correct_crc, 0x800D);

        /* SAP In */
        if (port_in_use(0)) {
                REG_WR_VECT(iop_sap_in, regi_iop_sap_in, rw_gio, 10, sap_in1);
                REG_WR_VECT(iop_sap_in, regi_iop_sap_in, rw_gio, 11, sap_in0);
                REG_WR_VECT(iop_sap_in, regi_iop_sap_in, rw_gio, 26, sap_in0);
        }
        if (port_in_use(1)) {
                REG_WR_VECT(iop_sap_in, regi_iop_sap_in, rw_gio, 14, sap_in1);
                REG_WR_VECT(iop_sap_in, regi_iop_sap_in, rw_gio, 15, sap_in0);
                REG_WR_VECT(iop_sap_in, regi_iop_sap_in, rw_gio, 30, sap_in0);
        }
        if (port_in_use(2)) {
                REG_WR_VECT(iop_sap_in, regi_iop_sap_in, rw_gio,  6, sap_in1);
                REG_WR_VECT(iop_sap_in, regi_iop_sap_in, rw_gio,  7, sap_in0);
                REG_WR_VECT(iop_sap_in, regi_iop_sap_in, rw_gio, 22, sap_in0);
        }
        if (port_in_use(3)) {
                REG_WR_VECT(iop_sap_in, regi_iop_sap_in, rw_gio,  2, sap_in1);
                REG_WR_VECT(iop_sap_in, regi_iop_sap_in, rw_gio,  3, sap_in0);
                REG_WR_VECT(iop_sap_in, regi_iop_sap_in, rw_gio, 18, sap_in0);
        }

        /* SAP Out */
        if (port_in_use(0)) {
                REG_WR_VECT(iop_sap_out, regi_iop_sap_out, rw_gio,  8, sap_out);
                REG_WR_VECT(iop_sap_out, regi_iop_sap_out, rw_gio,  9, sap_out);
        }
        if (port_in_use(1)) {
                REG_WR_VECT(iop_sap_out, regi_iop_sap_out, rw_gio, 12, sap_out);
                REG_WR_VECT(iop_sap_out, regi_iop_sap_out, rw_gio, 13, sap_out);
        }
        if (port_in_use(2)) {
                REG_WR_VECT(iop_sap_out, regi_iop_sap_out, rw_gio,  4, sap_out);
                REG_WR_VECT(iop_sap_out, regi_iop_sap_out, rw_gio,  5, sap_out);
        }
        if (port_in_use(3)) {
                REG_WR_VECT(iop_sap_out, regi_iop_sap_out, rw_gio,  0, sap_out);
                REG_WR_VECT(iop_sap_out, regi_iop_sap_out, rw_gio,  1, sap_out);
        }
        /* invert OE to PHY (active low) */
        sap_out.out_logic = regk_iop_sap_out_inv;
        if (port_in_use(0))
                REG_WR_VECT(iop_sap_out, regi_iop_sap_out, rw_gio, 24, sap_out);
        if (port_in_use(1))
                REG_WR_VECT(iop_sap_out, regi_iop_sap_out, rw_gio, 28, sap_out);
        if (port_in_use(2))
                REG_WR_VECT(iop_sap_out, regi_iop_sap_out, rw_gio, 20, sap_out);
        if (port_in_use(3))
                REG_WR_VECT(iop_sap_out, regi_iop_sap_out, rw_gio, 16, sap_out);

        /* initial configuration of GIOs */
        if (port_in_use(0))
                port_gio_config(0, 0);
        if (port_in_use(1))
                port_gio_config(1, 0);
        if (port_in_use(2))
                port_gio_config(2, 0);
        if (port_in_use(3))
                port_gio_config(3, 0);

        /* enable output for GIOs */
        mask = 0;
        gio_mask = REG_RD(iop_sw_cfg, regi_iop_sw_cfg, rw_gio_mask);
        gio_oe_mask = REG_RD(iop_sw_cfg, regi_iop_sw_cfg, rw_gio_oe_mask);
        gio_oe_set_mask = REG_RD(
                iop_sw_cpu, regi_iop_sw_cpu, rw_gio_oe_set_mask);
        if (port_in_use(0))
                mask |= PORT_GIO_OUT_ALL(0);
        if (port_in_use(1))
                mask |= PORT_GIO_OUT_ALL(1);
        if (port_in_use(2))
                mask |= PORT_GIO_OUT_ALL(2);
        if (port_in_use(3))
                mask |= PORT_GIO_OUT_ALL(3);
        gio_mask.val |= mask;
        gio_oe_mask.val |= mask;
        gio_oe_set_mask.val |= mask;
        REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_gio_mask, gio_mask);
        REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_gio_oe_mask, gio_oe_mask);
        REG_WR(iop_sw_cpu, regi_iop_sw_cpu, rw_gio_oe_set_mask, 
               gio_oe_set_mask);

        /* SOF and EOF2 Timers */
        switch (INST(frame_timer_grp)) {
        case regi_iop_timer_grp0:
                tmr_grp0_cfg = 
                        REG_RD(iop_sw_cfg, regi_iop_sw_cfg, rw_timer_grp0_cfg);
                tmr_grp0_cfg.ext_clk = regk_iop_sw_cfg_clk12;
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_timer_grp0_cfg, 
                       tmr_grp0_cfg);
                REG_WR_INT(iop_timer_grp, regi_iop_timer_grp0, rw_intr_mask,
                           1 << EOF2_TMR);
                break;
        case regi_iop_timer_grp1:
                tmr_grp1_cfg = 
                        REG_RD(iop_sw_cfg, regi_iop_sw_cfg, rw_timer_grp1_cfg);
                tmr_grp1_cfg.ext_clk = regk_iop_sw_cfg_clk12;
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_timer_grp1_cfg, 
                       tmr_grp1_cfg);
                REG_WR_INT(iop_timer_grp, regi_iop_timer_grp1, rw_intr_mask,
                           1 << EOF2_TMR);
                break;
        default:
                BUG();
        }
        REG_WR(iop_timer_grp, INST(frame_timer_grp), rw_cfg, tmr_grp_cfg);
        REG_WR(iop_timer_grp, INST(frame_timer_grp), rw_half_period, 
               half_period);
        REG_WR_INT(iop_timer_grp, INST(frame_timer_grp), rw_half_period_len,
                   1);
        REG_WR_VECT(iop_timer_grp, INST(frame_timer_grp), rw_tmr_cfg, 
                    SOF_TMR, sof_tmr_cfg);
        REG_WR_VECT(iop_timer_grp, INST(frame_timer_grp), rw_tmr_len,
                    SOF_TMR, sof_tmr_len);
        REG_WR_VECT(iop_timer_grp, INST(frame_timer_grp), rw_tmr_cfg, 
                    EOF2_TMR, eof2_tmr_cfg);
        REG_WR_VECT(iop_timer_grp, INST(frame_timer_grp), rw_tmr_len,
                    EOF2_TMR, eof2_tmr_len);
        REG_WR(iop_timer_grp, INST(frame_timer_grp), rw_cmd, tmr_grp_cmd_rst);
        REG_WR(iop_timer_grp, INST(frame_timer_grp), rw_cmd, tmr_grp_cmd_en);
        /* Timer used to count received bytes during IN transaction */
        /* Use SPU GIO_OUT7 as clock */
        switch (INST(rx_cnt_timer_grp)) {
        case regi_iop_timer_grp2:
                tmr_grp2_cfg = 
                        REG_RD(iop_sw_cfg, regi_iop_sw_cfg, rw_timer_grp2_cfg);
                tmr_grp2_cfg.ext_clk = regk_iop_sw_cfg_spu0_gio7;
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_timer_grp2_cfg, 
                       tmr_grp2_cfg);
                break;
        case regi_iop_timer_grp3:
                tmr_grp3_cfg = 
                        REG_RD(iop_sw_cfg, regi_iop_sw_cfg, rw_timer_grp3_cfg);
                tmr_grp3_cfg.ext_clk = regk_iop_sw_cfg_spu1_gio7;
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_timer_grp3_cfg, 
                       tmr_grp3_cfg);
                break;
        default:
                BUG();
        }
        REG_WR(iop_timer_grp, INST(rx_cnt_timer_grp), rw_cfg, tmr_grp_cfg);
        REG_WR(iop_timer_grp, INST(rx_cnt_timer_grp), rw_half_period, 
               half_period);
        REG_WR_INT(iop_timer_grp, INST(rx_cnt_timer_grp), rw_half_period_len, 
                   1);
        REG_WR_VECT(iop_timer_grp, INST(rx_cnt_timer_grp), rw_tmr_cfg,
                    RX_CNT_TMR, rx_cnt_tmr_cfg);
        
        /*
         * Set owners 
         */

        switch (INST(spu)) {
        case regi_iop_spu0:
                spu = regk_iop_sw_cfg_spu0;
                break;
        case regi_iop_spu1:
                spu = regk_iop_sw_cfg_spu1;
                break;
        default:
                BUG();
        }

        /* MPU owns SPU */
        switch (INST(spu)) {
        case regi_iop_spu0:
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_spu0_owner, 
                       spu0_owner);  
                break;
        case regi_iop_spu1:
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_spu1_owner, 
                       spu1_owner);  
                break;
        default:
                BUG();
        }               

        /* MPU owns DMC_IN */
        switch (INST(dmc_in)) {
        case regi_iop_dmc_in0:
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_dmc_in0_owner, 
                       dmc_in0_owner);  
                break;
        case regi_iop_dmc_in1:
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_dmc_in1_owner, 
                       dmc_in1_owner);  
                break;
        default:
                BUG();
        }
        
        /* MPU owns DMC_OUT */
        switch (INST(dmc_out)) {
        case regi_iop_dmc_out0:
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_dmc_out0_owner, 
                       dmc_out0_owner); 
                break;
        case regi_iop_dmc_out1:
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_dmc_out1_owner, 
                       dmc_out1_owner);  
                break;
        default:
                BUG();
        }

        /* MPU owns FIFO_IN */
        switch (INST(fifo_in)) {
        case regi_iop_fifo_in0:
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_fifo_in0_owner, 
                       fifo_in0_owner);
                break;
        case regi_iop_fifo_in1:
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_fifo_in1_owner, 
                       fifo_in1_owner);
                break;
        default:
                BUG();
        }

        /* SPU owns FIFO_OUT */
        switch (INST(fifo_out)) {
        case regi_iop_fifo_out0:
                fifo_out0_owner.cfg = spu;
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_fifo_out0_owner, 
                       fifo_out0_owner);
                break;
        case regi_iop_fifo_out1:
                fifo_out1_owner.cfg = spu;
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_fifo_out1_owner,
                       fifo_out1_owner);  
                break;
        default:
                BUG();
        }

        /* MPU owns FIFO_OUT_EXTRA */
        switch (INST(fifo_out_extra)) {
        case regi_iop_fifo_out0_extra:
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_fifo_out0_extra_owner,
                       fifo_out0_extra_owner);  
                break;
        case regi_iop_fifo_out1_extra:
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_fifo_out1_extra_owner,
                       fifo_out1_extra_owner);  
                break;
        default:
                BUG();
        }

        /* SPU owns SCRC_OUT */
        switch (INST(scrc_out)) {
        case regi_iop_scrc_out0:
                scrc_out0_owner.cfg = spu;
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_scrc_out0_owner, 
                       scrc_out0_owner);  
                break;
        case regi_iop_scrc_out1:
                scrc_out1_owner.cfg = spu;
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_scrc_out1_owner, 
                       scrc_out1_owner);  
                break;
        default:
                BUG();
        }

        /* SPU owns CRC_PAR */
        switch (INST(crc_par)) {
        case regi_iop_crc_par0:
                crc_par0_owner.cfg = spu;
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_crc_par0_owner, 
                       crc_par0_owner);  
                break;
        case regi_iop_crc_par1: 
                crc_par1_owner.cfg = spu;
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_crc_par1_owner, 
                       crc_par1_owner);  
                break;
        default:
                BUG();
        }

        /* MPU owns frame timers */
        switch (INST(frame_timer_grp)) {
        case regi_iop_timer_grp0:
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_timer_grp0_owner, 
                       timer_grp0_owner);
                break;
        case regi_iop_timer_grp1:
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_timer_grp1_owner, 
                       timer_grp1_owner);
                break;
        default:
                BUG();
        }
        
        /* MPU owns timer used to count received bytes during IN transaction */
        switch (INST(rx_cnt_timer_grp)) {
        case regi_iop_timer_grp2:
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_timer_grp2_owner, 
                       timer_grp2_owner);
                break;
        case regi_iop_timer_grp3:
                REG_WR(iop_sw_cfg, regi_iop_sw_cfg, rw_timer_grp3_owner, 
                       timer_grp3_owner);
                break;
        default:
                BUG();
        }
}

/* reset processors firmware and driver */
int iop_usb_reset(void)
{
        reg_iop_spu_rw_ctrl spu_ctrl = {
                .en  = regk_iop_spu_no,
                .fsm = regk_iop_spu_no,
        };

        /* halt SPU and MPU */
        REG_WR(iop_spu, INST(spu), rw_ctrl, spu_ctrl);
        if (mpu_halt() != 0)
                return IOP_USB_ERR_TIMEOUT;

        return IOP_USB_OK;
}

/* start execution */
int iop_usb_start(int intr_mask)
{
        int intr0_mask;
        u32 fw_id;

        BUG_ON(iop_usb_cfg.ports < 0);

        /* start with all ports powered off */
        port_power = 0;

        /* initialize DMA data structure */
        init_dma();
        
        /* validate the loaded firmware */
        if (read_mpu_mem(MPU_ADDR_FW_ID, &fw_id) != 0)
                return IOP_USB_ERR_TIMEOUT;
        if (!CHECK_FW_ID(fw_id, MPU, iop_usb_cfg.dma_map))
                return IOP_USB_ERR_BAD_FW;

        /* store information about included ports in MPU memory */
        if (write_mpu_mem(MPU_ADDR_PORTS, iop_usb_cfg.ports))
                return IOP_USB_ERR_TIMEOUT;

        /* start the MPU */
        if (mpu_start() != 0)
                return IOP_USB_ERR_TIMEOUT;
                
        /* interrupts to CPU */
        intr0_mask = REG_RD_INT(iop_sw_cpu, regi_iop_sw_cpu, rw_intr0_mask);
        intr0_mask |= intr_mask & CPU_IRQ_MASK;
        REG_WR_INT(iop_sw_cpu, regi_iop_sw_cpu, rw_intr0_mask, intr0_mask);

        return IOP_USB_OK;
}

/* get current frame number */
int iop_usb_get_frame(void)
{
        u32 data;
        if (read_mpu_mem(MPU_ADDR_FRAME_NUMBER, &data) != 0)
                return -1;
        return data & 0x7ff;
}

/* get port status and port change fields */
int iop_usb_port_stat(unsigned int port, u16 *wPortStatus, u16 *wPortChange)
{
        u32 data;

        BUG_ON(port < 0 || port >= IOP_USB_ROOT_HUB_PORTS);
        if (!port_in_use(port))
                return IOP_USB_ERR_INVAL;
        if (read_mpu_mem(mpu_addr_port_stat(port), &data) != 0)
                return IOP_USB_ERR_TIMEOUT;
        if (wPortStatus) {
                *wPortStatus = data & 0xffff;
                if (port_power & (1 << port))
                        *wPortStatus |= (1 << IOP_USB_PORT_POWER);
        }
        if (wPortChange)
                *wPortChange = (data >> 16) & 0xff;
        return IOP_USB_OK;
}

/* set port status feature */
int iop_usb_set_port_feat(unsigned int port, unsigned int feat)
{
        u16 wPortStatus;                
        int low_speed;

        BUG_ON(port < 0 || port >= IOP_USB_ROOT_HUB_PORTS);

        if (!port_in_use(port))
                return IOP_USB_ERR_INVAL;

        switch (feat) {
        case IOP_USB_PORT_POWER:
                /* enable power to port, not supported on FS testcard
                 * with D38 removed */
                port_power |= (1 << port);
                return IOP_USB_OK;
        case IOP_USB_PORT_RESET:
                if (iop_usb_port_stat(port, &wPortStatus, NULL) != IOP_USB_OK)
                        return IOP_USB_ERR_TIMEOUT;
                low_speed = wPortStatus & (1 << IOP_USB_PORT_LOW_SPEED);
                port_gio_config(port, low_speed);
                break;
        case IOP_USB_PORT_SUSPEND:
                break;
        default:
                return IOP_USB_ERR_INVAL;
        }
        if (mpu_rh_port_request(IOP_USB_SET_FEATURE, port, feat) != 0)
                return IOP_USB_ERR_TIMEOUT;
        return IOP_USB_OK;
}

/* clear port status or port status change feature */
int iop_usb_clr_port_feat(unsigned int port, unsigned int feat)
{
        BUG_ON(port < 0 || port >= IOP_USB_ROOT_HUB_PORTS);
        if (!port_in_use(port))
                return IOP_USB_ERR_INVAL;

        switch (feat) {
        case IOP_USB_PORT_POWER:
                /* disable power to port, not supported on FS testcard
                 * with D38 removed */
                port_power &= ~(1 << port);
                return IOP_USB_OK;
        case IOP_USB_PORT_ENABLE:
        case IOP_USB_PORT_SUSPEND:      
                break;
        case IOP_USB_C_PORT_CONNECTION:
        case IOP_USB_C_PORT_ENABLE:
        case IOP_USB_C_PORT_SUSPEND:
        case IOP_USB_C_PORT_OVERCURRENT:
        case IOP_USB_C_PORT_RESET:
                /* clear port status change bit */
                break;
        default:
                return IOP_USB_ERR_INVAL;
        }
        if (mpu_rh_port_request(IOP_USB_CLEAR_FEATURE, port, feat) != 0)
                return IOP_USB_ERR_TIMEOUT;
        return IOP_USB_OK;
}

/* get active interrupts */
int iop_usb_active_irqs(void)
{
        int irqs = REG_RD_INT(iop_sw_cpu, regi_iop_sw_cpu, r_masked_intr0);
        irqs &= CPU_IRQ_MASK;
        REG_WR_INT(iop_sw_cpu, regi_iop_sw_cpu, rw_ack_intr0, irqs);
        return irqs;
}

/* get SPU number used */
int iop_usb_spu_nr(void)
{
        if (iop_usb_cfg.dma_map < 0)
                return -1;
        switch (INST(spu)) {
        case regi_iop_spu0:
                return 0;
        case regi_iop_spu1:
                return 1;
        default:
                return -1;
        }
}

/* get DMA mapping used by the loaded firmware */
int iop_usb_dma_map(void)
{
        u32 fw_id;

        if (read_mpu_mem(MPU_ADDR_FW_ID, &fw_id) != 0)
                return -1;
        return (fw_id & FW_ID_DMAMAP_MASK) >> FW_ID_DMAMAP_BIT;
}

---