os/linux-2.6-tag--devboard-R2_10-4/drivers/net/cris/eth_v32.c

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/*
 * Driver for the ETRAX FS network controller.
 *
 * Copyright (c) 2003-2006 Axis Communications AB.
 */

#include <linux/module.h>

#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/delay.h>
#include <linux/types.h>
#include <linux/fcntl.h>
#include <linux/interrupt.h>
#include <linux/ptrace.h>
#include <linux/ioport.h>
#include <linux/in.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/cpufreq.h>

#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/ethtool.h>
#include <linux/mii.h>

#include <asm/io.h>             /* LED_* I/O functions */
#include <asm/irq.h>
#include <asm/arch/hwregs/reg_map.h>
#include <asm/arch/hwregs/reg_rdwr.h>
#include <asm/arch/hwregs/dma.h>
#include <asm/arch/hwregs/eth_defs.h>
#ifdef CONFIG_ETRAXFS
#include <asm/arch/hwregs/config_defs.h>
#else
#include <asm/arch/hwregs/clkgen_defs.h>
#endif
#include <asm/arch/hwregs/intr_vect_defs.h>
#include <asm/system.h>
#include <asm/bitops.h>
#include <asm/ethernet.h>
#include <asm/arch/dma.h>
#include <asm/arch/intmem.h>
#include <asm/arch/pinmux.h>

#include "eth_v32.h"

#ifndef CONFIG_ETRAXFS
#define ETH0_INTR_VECT ETH_INTR_VECT
#define ETH1_INTR_VECT ETH_INTR_VECT
#define regi_eth0 regi_eth
#define regi_eth1 regi_
#endif

#define DEBUG(x)
#define GET_BIT(bit,val)   (((val) >> (bit)) & 0x01)

/* Toggle network LEDs on/off at runtime */
static int use_network_leds = 1;

static void update_rx_stats(struct crisv32_ethernet_local *np);
static void update_tx_stats(struct crisv32_ethernet_local *np); 
static int crisv32_eth_poll(struct net_device *dev, int *budget);
static void crisv32_eth_setup_controller(struct net_device *dev);
static int  crisv32_eth_request_irqdma(struct net_device *dev);
static void crisv32_ethernet_bug(struct net_device *dev);

/*
 * The name of the card. Is used for messages and in the requests for
 * io regions, irqs and dma channels.
 */
static const char *cardname = "ETRAX FS built-in ethernet controller";

static int autoneg_normal = 1;

/* Some chipset needs special care. */
struct transceiver_ops transceivers[] = {
        {0x1018, broadcom_check_speed, broadcom_check_duplex},
        /* TDK 2120 and TDK 2120C */
        {0xC039, tdk_check_speed, tdk_check_duplex}, 
        {0x039C, tdk_check_speed, tdk_check_duplex},    
        /* Intel LXT972A*/
        {0x04de, intel_check_speed, intel_check_duplex},
        /* National Semiconductor DP83865 */
        {0x0017, national_check_speed, national_check_duplex},
        /* Vitesse VCS8641 */
        {0x01c1, vitesse_check_speed, vitesse_check_duplex},
        /* Generic, must be last. */
        {0x0000, generic_check_speed, generic_check_duplex}
};

static struct net_device *crisv32_dev[2];
static struct crisv32_eth_leds *crisv32_leds[3];

/* Default MAC address for interface 0.
 * The real one will be set later. */
static struct sockaddr default_mac_iface0 = 
  {0, {0x00, 0x40, 0x8C, 0xCD, 0x00, 0x00}};

#ifdef CONFIG_CPU_FREQ
static int
crisv32_ethernet_freq_notifier(struct notifier_block *nb, unsigned long val,
                               void *data);

static struct notifier_block crisv32_ethernet_freq_notifier_block = {
        .notifier_call  = crisv32_ethernet_freq_notifier
};
#endif

/*
 * mask in and out tx/rx interrupts.
 */
static inline void crisv32_disable_tx_ints(struct crisv32_ethernet_local *np)
{
        reg_dma_rw_intr_mask intr_mask_tx = { .data = regk_dma_no };
        REG_WR(dma, np->dma_out_inst, rw_intr_mask, intr_mask_tx);
}

static inline void crisv32_enable_tx_ints(struct crisv32_ethernet_local *np)
{
        reg_dma_rw_intr_mask intr_mask_tx = { .data = regk_dma_yes };
        REG_WR(dma, np->dma_out_inst, rw_intr_mask, intr_mask_tx);
}

static inline void crisv32_disable_rx_ints(struct crisv32_ethernet_local *np)
{
        reg_dma_rw_intr_mask intr_mask_rx = { .in_eop = regk_dma_no };
        REG_WR(dma, np->dma_in_inst, rw_intr_mask, intr_mask_rx);
}

static inline void crisv32_enable_rx_ints(struct crisv32_ethernet_local *np)
{
        reg_dma_rw_intr_mask intr_mask_rx = { .in_eop = regk_dma_yes };
        REG_WR(dma, np->dma_in_inst, rw_intr_mask, intr_mask_rx);
}

/* start/stop receiver */
static inline void crisv32_start_receiver(struct crisv32_ethernet_local *np)
{
        reg_eth_rw_rec_ctrl rec_ctrl;
        
        rec_ctrl = REG_RD(eth, np->eth_inst, rw_rec_ctrl);
        rec_ctrl.ma0 = regk_eth_yes;
        rec_ctrl.broadcast = regk_eth_rec;
        REG_WR(eth, np->eth_inst, rw_rec_ctrl, rec_ctrl);
}

static inline void crisv32_stop_receiver(struct crisv32_ethernet_local *np)
{
        reg_eth_rw_rec_ctrl rec_ctrl;

        rec_ctrl = REG_RD(eth, np->eth_inst, rw_rec_ctrl);
        rec_ctrl.ma0 = regk_eth_no;
        rec_ctrl.broadcast = regk_eth_discard;
        REG_WR(eth, np->eth_inst, rw_rec_ctrl, rec_ctrl);
}

static int __init
crisv32_eth_request_irqdma(struct net_device *dev)
{
        struct crisv32_ethernet_local *np = netdev_priv(dev);
        
        /* Allocate IRQs and DMAs. */
        if (np->eth_inst == regi_eth0) {
                if (request_irq(DMA0_INTR_VECT, crisv32tx_eth_interrupt, 
                                0, cardname, dev)) {
                        return -EAGAIN;
                }

                if (request_irq(DMA1_INTR_VECT, crisv32rx_eth_interrupt,
                                IRQF_SAMPLE_RANDOM, cardname, dev)) {
                        goto err0_1; 
                }
                
                if (crisv32_request_dma(0, cardname, DMA_VERBOSE_ON_ERROR,
                                        12500000, dma_eth0))
                        goto err0_2;
                
                if (crisv32_request_dma(1, cardname, DMA_VERBOSE_ON_ERROR,
                                        12500000, dma_eth0))
                        goto err0_3;
                
                if (request_irq(ETH0_INTR_VECT, crisv32nw_eth_interrupt, 0,
                                cardname, dev)) {
                        crisv32_free_dma(1);
                  err0_3:
                        crisv32_free_dma(0);
                  err0_2:
                        free_irq(DMA1_INTR_VECT, dev);
                  err0_1:
                        free_irq(DMA0_INTR_VECT, dev);
                        return -EAGAIN;
                }
        } else {
                if (request_irq(DMA6_INTR_VECT, crisv32tx_eth_interrupt,
                                0, cardname, dev))
                        return -EAGAIN;
                
                if (request_irq(DMA7_INTR_VECT, crisv32rx_eth_interrupt,
                                IRQF_SAMPLE_RANDOM, cardname, dev))
                        goto err1_1;

                if (crisv32_request_dma(6, cardname, DMA_VERBOSE_ON_ERROR,
                                        0, dma_eth1))
                        goto err1_2;

                if (crisv32_request_dma(7, cardname, DMA_VERBOSE_ON_ERROR,
                                        0, dma_eth1))
                        goto err1_3;

                if (request_irq(ETH1_INTR_VECT, crisv32nw_eth_interrupt, 0,
                                cardname, dev)) {
                        crisv32_free_dma(7);
                  err1_3:
                        crisv32_free_dma(6);
                  err1_2:
                        free_irq(DMA7_INTR_VECT, dev);
                  err1_1:
                        free_irq(DMA6_INTR_VECT, dev);
                        return -EAGAIN;
                }
        }
        return 0;
}

static void __init
crisv32_eth_setup_controller(struct net_device *dev)
{
        struct crisv32_ethernet_local *np = netdev_priv(dev);
        
        reg_eth_rw_tr_ctrl tr_ctrl = {
                .retry = regk_eth_yes,
                .pad = regk_eth_yes,
                .crc = regk_eth_yes
        };
        
        reg_eth_rw_rec_ctrl rec_ctrl = {
                .ma0 = regk_eth_no,       /* enable at open() */
                .broadcast = regk_eth_no,
                .max_size = regk_eth_size1522
        };
                
        reg_eth_rw_ga_lo ga_lo = { 0 };
        reg_eth_rw_ga_hi ga_hi = { 0 };

        reg_eth_rw_gen_ctrl gen_ctrl = {
          .phy = regk_eth_mii_clk,
          .flow_ctrl = regk_eth_yes
        };

        /* 
         * Initialize group address registers to make sure that no
         * unwanted addresses are matched.
         */
        REG_WR(eth, np->eth_inst, rw_ga_lo, ga_lo);
        REG_WR(eth, np->eth_inst, rw_ga_hi, ga_hi);
        
        /* Configure receiver and transmitter */
        REG_WR(eth, np->eth_inst, rw_rec_ctrl, rec_ctrl);
        REG_WR(eth, np->eth_inst, rw_tr_ctrl, tr_ctrl);

        /* Enable ethernet controller with mii clk. */
        REG_WR(eth, np->eth_inst, rw_gen_ctrl, gen_ctrl);
        gen_ctrl.en = regk_eth_yes;
        REG_WR(eth, np->eth_inst, rw_gen_ctrl, gen_ctrl);
        
        /* keep reset low (RESET_LEN) */
        udelay(500);

        /* done */
        
#ifdef CONFIG_ETRAXFS
        reg_config_rw_pad_ctrl pad_ctrl;
        pad_ctrl = REG_RD(config, regi_config, rw_pad_ctrl);
        pad_ctrl.phyrst_n = 1;
        REG_WR(config, regi_config, rw_pad_ctrl, pad_ctrl);
#else
        gen_ctrl.phyrst_n = 1;
        REG_WR(eth, np->eth_inst, rw_gen_ctrl, gen_ctrl);
#endif

        /* Let the PHY reset (RESET_WAIT) */
        udelay(200);
                
        if(crisv32_eth_probe_transceiver(dev)) {
                printk("%s: No transceiver found, removing interface\n", 
                       dev->name);
                unregister_netdev(dev);
                /* We should probably do more here... */
        }
}

static void
crisv32_eth_reset_rings(struct net_device *dev)
{
        struct crisv32_ethernet_local *np = netdev_priv(dev);
        int i;

        /* free un-handled tx packets */       
        while(np->txpackets
              || np->catch_tx_desc != np->active_tx_desc) {
                np->txpackets--;
                if (np->catch_tx_desc->skb)
                        dev_kfree_skb(np->catch_tx_desc->skb);
                
                np->catch_tx_desc->skb = 0;
                np->catch_tx_desc =
                        phys_to_virt((int)np->catch_tx_desc->descr.next);
        } while (np->catch_tx_desc != np->active_tx_desc);
        WARN_ON(np->txpackets != 0);
        np->txpackets = 0;

        /* cleanup the rx-ring */
        for (i = 0; i < NBR_RX_DESC; i++) {
                struct sk_buff *skb;
                skb = np->dma_rx_descr_list[i].skb;
                if (!skb
                    || (np->dma_rx_descr_list[i].descr.buf !=
                        (void *)virt_to_phys(skb->data)))
                {                      
                        printk("%s:%d: damaged rx-ring! "
                               "i=%d skb=%p %lx %lx %p %p\n",
                               __func__, __LINE__, i,
                               skb,
                               virt_to_phys(skb->data),
                               virt_to_phys(skb->data + MAX_MEDIA_DATA_SIZE),
                               np->dma_rx_descr_list[i].descr.buf,
                               np->dma_rx_descr_list[i].descr.after);
                        WARN_ON(1);
                        crisv32_ethernet_bug(dev);                      
                        if (skb)
                                dev_kfree_skb(skb);
                        skb = dev_alloc_skb(MAX_MEDIA_DATA_SIZE);
                        np->dma_rx_descr_list[i].skb = skb;
                        np->dma_rx_descr_list[i].descr.buf =
                                (char*)virt_to_phys(skb->data);
                }
                np->dma_rx_descr_list[i].descr.after =
                        (char*)virt_to_phys(skb->data
                                            + MAX_MEDIA_DATA_SIZE);
                np->dma_rx_descr_list[i].descr.eol = 0;
                np->dma_rx_descr_list[i].descr.in_eop = 0;
                /* Workaround cache bug */
                flush_dma_descr(&np->dma_rx_descr_list[i].descr, 1); 
        }
        
        /* reset rx-ring */
        np->active_rx_desc = &np->dma_rx_descr_list[0];
        np->prev_rx_desc = &np->dma_rx_descr_list[NBR_RX_DESC - 1];
        np->last_rx_desc = np->prev_rx_desc;
        np->dma_rx_descr_list[NBR_RX_DESC - 1].descr.eol = 1;
        /* ready to accept new packets.  */
        np->new_rx_package = 1;
        
        /* reset tx-ring */
        np->dma_tx_descr_list[0].descr.buf =
                np->dma_tx_descr_list[0].descr.after = 0;
        np->dma_rx_descr_list[i].descr.in_eop = 0;
        np->dma_tx_descr_list[0].descr.eol = 1;
        
        np->active_tx_desc = &np->dma_tx_descr_list[0];
        np->prev_tx_desc = &np->dma_tx_descr_list[NBR_TX_DESC - 1];
        np->catch_tx_desc = &np->dma_tx_descr_list[0];
        
        /* Fill context descriptors. */
        np->ctxt_in.next = 0;
        np->ctxt_in.saved_data =
                (void *)virt_to_phys(&np->active_rx_desc->descr);
        np->ctxt_in.saved_data_buf = np->active_rx_desc->descr.buf;
                
        np->ctxt_out.next = 0;
        np->ctxt_out.saved_data =
                (void *)virt_to_phys(&np->dma_tx_descr_list[0].descr);
}

/*
 * Really advance the receive ring. RX interrupts must be off.
 */
static void
__crisv32_eth_rx_ring_advance(struct crisv32_ethernet_local *np)
{
        if (np->newbuf)
                np->active_rx_desc->descr.buf = (void *) np->newbuf;
        np->active_rx_desc->descr.after =
                np->active_rx_desc->descr.buf + MAX_MEDIA_DATA_SIZE;    
        np->active_rx_desc->descr.eol = 1;
        np->active_rx_desc->descr.in_eop = 0;
        np->active_rx_desc = phys_to_virt((int)np->active_rx_desc->descr.next);
        barrier();
        np->prev_rx_desc->descr.eol = 0;

        /* Workaround cache bug.  */
        flush_dma_descr(&np->prev_rx_desc->descr, 0);
        np->prev_rx_desc = phys_to_virt((int)np->prev_rx_desc->descr.next);
        flush_dma_descr(&np->prev_rx_desc->descr, 1);
}

/*
 * Advance the receive ring. RX interrupts must be off.
 */
static inline void
crisv32_eth_rx_ring_advance(struct crisv32_ethernet_local *np)
{
        /*
         * When the input DMA reaches eol precaution must be taken, otherwise
         * the DMA could stop. The problem occurs if the eol flag is re-placed
         * on the descriptor that the DMA stands on before the DMA proceed to
         * the next descriptor. This case could, for example, happen if there
         * is a traffic burst and then the network goes silent. To prevent this
         * we make sure that we do not set the eol flag on the descriptor that
         * the DMA stands on.
         */
        if(virt_to_phys(&np->active_rx_desc->descr) !=
           REG_RD_INT(dma, np->dma_in_inst, rw_saved_data)) {
                /* Now really advance the ring one step.  */
                __crisv32_eth_rx_ring_advance(np);
                if ((((crisv32_eth_descr*)(phys_to_virt((int)np->active_rx_desc->descr.next)))->descr.in_eop) && !(np->active_rx_desc->descr.in_eop)) __crisv32_eth_rx_ring_advance(np);
        } else {
                /* delay the advancing of the ring.  */
                np->new_rx_package = 0;
        }
}

static void __init
crisv32_eth_init_rings(struct net_device *dev)
{
        struct crisv32_ethernet_local *np = netdev_priv(dev);
        int i;
        
        /* Initialise receive descriptors for interface. */
        for (i = 0; i < NBR_RX_DESC; i++) {
                struct sk_buff *skb = dev_alloc_skb(MAX_MEDIA_DATA_SIZE);

                np->dma_rx_descr_list[i].skb = skb;
                np->dma_rx_descr_list[i].descr.buf =
                        (char*)virt_to_phys(skb->data);
                np->dma_rx_descr_list[i].descr.after =
                    (char*)virt_to_phys(skb->data + MAX_MEDIA_DATA_SIZE);

                np->dma_rx_descr_list[i].descr.eol = 0;
                np->dma_rx_descr_list[i].descr.in_eop = 0;
                np->dma_rx_descr_list[i].descr.next =
                    (void *) virt_to_phys(&np->dma_rx_descr_list[i + 1].descr);
        }
        /* bend the list into a ring */ 
        np->dma_rx_descr_list[NBR_RX_DESC - 1].descr.next =
                (void *) virt_to_phys(&np->dma_rx_descr_list[0].descr);
        
        /* Initialize transmit descriptors. */
        for (i = 0; i < NBR_TX_DESC; i++) {
                np->dma_tx_descr_list[i].descr.wait = 1;
                np->dma_tx_descr_list[i].descr.eol = 0;
                np->dma_tx_descr_list[i].descr.out_eop = 0;
                np->dma_tx_descr_list[i].descr.next =
                        (void*)virt_to_phys(&np->dma_tx_descr_list[i+1].descr);
        }
        /* bend the list into a ring */
        np->dma_tx_descr_list[NBR_TX_DESC - 1].descr.next =
                (void *) virt_to_phys(&np->dma_tx_descr_list[0].descr);

        crisv32_eth_reset_rings(dev);
}

static void __init
crisv32_init_leds(int ledgrp, struct net_device* dev)
{
        struct timer_list timer_init = TIMER_INITIALIZER(NULL, 0, 0);
        struct crisv32_ethernet_local *np = netdev_priv(dev);

        /* Use already allocated led grp if initialized */
        if (crisv32_leds[ledgrp] != NULL) {
                np->leds = crisv32_leds[ledgrp];
                return;
        }

        crisv32_leds[ledgrp] = kmalloc(sizeof(struct crisv32_eth_leds),
                                       GFP_KERNEL);

        crisv32_leds[ledgrp]->ledgrp = ledgrp;
        crisv32_leds[ledgrp]->led_active = 0;
        /* NOTE: Should this value be set to zero as the jiffies timer 
           can wrap? */
        crisv32_leds[ledgrp]->led_next_time = jiffies;

        crisv32_leds[ledgrp]->clear_led_timer = timer_init;
        crisv32_leds[ledgrp]->clear_led_timer.function = 
                crisv32_clear_network_leds;
        crisv32_leds[ledgrp]->clear_led_timer.data = (unsigned long) dev;

        spin_lock_init(&crisv32_leds[ledgrp]->led_lock);

        np->leds = crisv32_leds[ledgrp];
}

static int __init
crisv32_ethernet_init(void)
{
        struct crisv32_ethernet_local *np;
        int ret = 0;

        printk("ETRAX FS 10/100MBit ethernet v0.01 (c)"
               " 2003 Axis Communications AB\n");

#ifdef CONFIG_CRIS_MACH_ARTPEC3
        {
                reg_clkgen_rw_clk_ctrl clk_ctrl = REG_RD(clkgen, regi_clkgen, 
                                                         rw_clk_ctrl);
                clk_ctrl.eth = clk_ctrl.dma0_1_eth = regk_clkgen_yes;  
                REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl);
        }
#endif
#ifdef CONFIG_ETRAX_ETHERNET_IFACE0
{
        int iface0 = 0;

#ifdef CONFIG_CRIS_MACH_ARTPEC3
        if (crisv32_pinmux_alloc_fixed(pinmux_eth))
                panic("Eth pinmux\n");
#ifdef CONFIG_ETRAX_ETHERNET_GBIT
        if (crisv32_pinmux_alloc_fixed(pinmux_geth))
                panic("Eth pinmux\n");
#endif
#endif
        
        if (!(crisv32_dev[iface0] = alloc_etherdev(sizeof *np)))
                return -ENOMEM;
        
        ret |= crisv32_ethernet_device_init(crisv32_dev[iface0]);
        
#if defined(CONFIG_ETRAX_ETH0_USE_LEDGRP0)
        crisv32_init_leds(LED_GRP_0,crisv32_dev[iface0]);
#elif defined(CONFIG_ETRAX_ETH0_USE_LEDGRP1)
        crisv32_init_leds(LED_GRP_1,crisv32_dev[iface0]);
#else
        crisv32_init_leds(LED_GRP_NONE,crisv32_dev[iface0]);
#endif

        np = (struct crisv32_ethernet_local *) crisv32_dev[iface0]->priv;
        np->eth_inst = regi_eth0;
        np->dma_out_inst = regi_dma0;
        np->dma_in_inst = regi_dma1;
        
        register_netdev(crisv32_dev[iface0]);
        
        /* Set up default MAC address */
        memcpy(crisv32_dev[iface0]->dev_addr, default_mac_iface0.sa_data, 6);
        crisv32_eth_set_mac_address(crisv32_dev[iface0], &default_mac_iface0);
        if (crisv32_eth_request_irqdma(crisv32_dev[iface0]))
                printk("%s: eth0 unable to allocate IRQ and DMA resources\n",
                       __func__);
        np->txpackets = 0;
        crisv32_eth_init_rings(crisv32_dev[iface0]);
        crisv32_eth_setup_controller(crisv32_dev[iface0]);
}
#endif /* CONFIG_ETRAX_ETHERNET_IFACE0 */

#ifdef CONFIG_ETRAX_ETHERNET_IFACE1
{
        int iface1 = 0;
        /* Default MAC address for interface 1.
         * The real one will be set later. */
        static struct sockaddr default_mac_iface1 = 
                {0, {0x00, 0x40, 0x8C, 0xCD, 0x00, 0x01}};

        if (crisv32_pinmux_alloc_fixed(pinmux_eth1))
                panic("Eth pinmux\n");

        /* Increase index to device array if interface 0 is enabled as well.*/
#ifdef CONFIG_ETRAX_ETHERNET_IFACE0
        iface1++;
#endif
        if (!(crisv32_dev[iface1] = alloc_etherdev(sizeof *np)))
                return -ENOMEM;
        
        ret |= crisv32_ethernet_device_init(crisv32_dev[iface1]);

#if defined(CONFIG_ETRAX_ETH1_USE_LEDGRP0)
        crisv32_init_leds(LED_GRP_0,crisv32_dev[iface1]);
#elif defined(CONFIG_ETRAX_ETH1_USE_LEDGRP1)
        crisv32_init_leds(LED_GRP_1,crisv32_dev[iface1]);
#else
        crisv32_init_leds(LED_GRP_NONE,crisv32_dev[iface1]);
#endif

        np = (struct crisv32_ethernet_local *) crisv32_dev[iface1]->priv;
        np->eth_inst = regi_eth1;
        np->dma_out_inst = regi_dma6;
        np->dma_in_inst = regi_dma7;
        
        register_netdev(crisv32_dev[iface1]);

        /* Set up default MAC address */
        memcpy(crisv32_dev[iface1]->dev_addr, default_mac_iface1.sa_data, 6);
        crisv32_eth_set_mac_address(crisv32_dev[iface1], &default_mac_iface1);
        
        if (crisv32_eth_request_irqdma(crisv32_dev[iface1]))
                printk("%s: eth1 unable to allocate IRQ and DMA resources\n",
                       __func__);
        np->txpackets = 0;
        crisv32_eth_init_rings(crisv32_dev[iface1]);
        crisv32_eth_setup_controller(crisv32_dev[iface1]);
}
#endif /* CONFIG_ETRAX_ETHERNET_IFACE1 */

#ifdef CONFIG_CPU_FREQ
        cpufreq_register_notifier(&crisv32_ethernet_freq_notifier_block,
                                  CPUFREQ_TRANSITION_NOTIFIER);
#endif

        return ret;
}

static int __init
crisv32_ethernet_device_init(struct net_device* dev)
{
        struct timer_list timer_init = TIMER_INITIALIZER(NULL, 0, 0);
        struct crisv32_ethernet_local *np;

        dev->base_addr = 0;     /* Just to have something to show. */

        /* we do our own locking */
        dev->features |= NETIF_F_LLTX;
        
        /* We use several IRQs and DMAs so just report 0 here. */
        dev->irq = 0;
        dev->dma = 0;

        /* 
         * Fill in our handlers so the network layer can talk to us in the
         * future. 
         */
        dev->open = crisv32_eth_open;
        dev->hard_start_xmit = crisv32_eth_send_packet;
        dev->stop = crisv32_eth_close;
        dev->get_stats = crisv32_get_stats;
        dev->set_multicast_list = crisv32_eth_set_multicast_list;
        dev->set_mac_address = crisv32_eth_set_mac_address;
        dev->ethtool_ops = &crisv32_ethtool_ops;
        dev->do_ioctl = crisv32_eth_ioctl;
        dev->set_config = crisv32_eth_set_config;
        dev->tx_timeout = crisv32_eth_tx_timeout;
#ifdef CONFIG_NET_POLL_CONTROLLER
        dev->poll_controller = crisv32_netpoll;
#endif
        /*
         * 8 skbs keeps the system very reponsive even under high load.
         * At 64 the system locks, pretty much the same way as without NAPI.
         * 
         * TODO: meassure with 2 interfaces
         */
        dev->weight = 8;
        dev->poll = crisv32_eth_poll;
        
        np = netdev_priv(dev);

        spin_lock_init(&np->lock);
        spin_lock_init(&np->transceiver_lock);
        
        /* Initialize speed indicator stuff. */
        np->current_speed = 10;
        np->current_speed_selection = 0;        /* Auto. */
        np->speed_timer = timer_init;
        np->speed_timer.expires = jiffies + NET_LINK_UP_CHECK_INTERVAL;
        np->speed_timer.data = (unsigned long) dev;
        np->speed_timer.function = crisv32_eth_check_speed;

        np->full_duplex = 0;
        np->current_duplex = autoneg;
        np->duplex_timer = timer_init;
        np->duplex_timer.expires = jiffies + NET_DUPLEX_CHECK_INTERVAL;
        np->duplex_timer.data = (unsigned long) dev;
        np->duplex_timer.function = crisv32_eth_check_duplex;
        
        return 0;
}

static int
crisv32_eth_open(struct net_device *dev)
{
        struct sockaddr mac_addr;
        reg_dma_rw_ack_intr ack_intr = { .data = 1,.in_eop = 1 };
        reg_eth_rw_clr_err clr_err = {.clr = regk_eth_yes};
        /*
         * dont interrupt us at any stat counter thresholds, only at urun
         * and exc_col.
         */
        int intr_mask_nw = 0x1800;
        int eth_ack_intr = 0xffff;
        struct crisv32_ethernet_local *np = netdev_priv(dev);

        spin_lock(&np->lock);
#ifdef CONFIG_CRIS_MACH_ARTPEC3
        np->gigabit_mode = 0;
#endif
        crisv32_disable_tx_ints(np);
        crisv32_disable_rx_ints(np);
        
        REG_WR(eth, np->eth_inst, rw_clr_err, clr_err);
        REG_WR_INT(eth, np->eth_inst, rw_ack_intr, eth_ack_intr);
        REG_WR_INT(eth, np->eth_inst, rw_intr_mask, intr_mask_nw);
        crisv32_eth_reset_rings(dev);
        
        /* Give the hardware an idea of what MAC address we want. */
        memcpy(mac_addr.sa_data, dev->dev_addr, dev->addr_len);
        crisv32_eth_set_mac_address(dev, &mac_addr);

        /* Enable irq and make sure that the irqs are cleared. */
        REG_WR(dma, np->dma_out_inst, rw_ack_intr, ack_intr);
        REG_WR(dma, np->dma_in_inst, rw_ack_intr, ack_intr);
        
        /* Prepare input DMA. */
        DMA_RESET(np->dma_in_inst);
        DMA_ENABLE(np->dma_in_inst);
#ifdef CONFIG_CRIS_MACH_ARTPEC3
        DMA_WR_CMD(np->dma_in_inst, regk_dma_set_w_size2);
#endif
        DMA_START_CONTEXT( np->dma_in_inst, virt_to_phys(&np->ctxt_in));
        DMA_CONTINUE(np->dma_in_inst);
        crisv32_enable_rx_ints(np);
        crisv32_start_receiver(np);     
        
        /* Prepare output DMA. */
        DMA_RESET(np->dma_out_inst);
        DMA_ENABLE(np->dma_out_inst);
#ifdef CONFIG_CRIS_MACH_ARTPEC3
        DMA_WR_CMD(np->dma_out_inst, regk_dma_set_w_size4);
#endif
        netif_start_queue(dev);
        crisv32_enable_tx_ints(np);
        
        /* Start duplex/speed timers */
        add_timer(&np->speed_timer);
        add_timer(&np->duplex_timer);   

        spin_unlock(&np->lock);
        /* 
         * We are now ready to accept transmit requests from the queueing
         * layer of the networking.
         */
        netif_carrier_on(dev);
        netif_poll_enable(dev);

        return 0;
}

static int
crisv32_eth_close(struct net_device *dev)
{
        reg_dma_rw_ack_intr ack_intr = {0};

        struct crisv32_ethernet_local *np = netdev_priv(dev);
        unsigned long flags;

        printk(KERN_INFO "Closing %s.\n", dev->name);
        spin_lock_irqsave(&np->lock, flags);

        /* stop the receiver before the DMA channels to avoid overruns. */
        crisv32_disable_rx_ints(np);
        netif_poll_disable(dev);
        crisv32_stop_receiver(np);
        
        netif_stop_queue(dev);

        /* Reset the TX DMA in case it has hung on something. */
        DMA_RESET(np->dma_in_inst);

        /* Stop DMA */
        DMA_STOP(np->dma_in_inst);
        DMA_STOP(np->dma_out_inst);

        /* Disable irq and make sure that the irqs are cleared. */
        crisv32_disable_tx_ints(np);
        ack_intr.data = 1;
        REG_WR(dma, np->dma_out_inst, rw_ack_intr, ack_intr);

        ack_intr.in_eop = 1;
        REG_WR(dma, np->dma_in_inst, rw_ack_intr, ack_intr);

        np->sender_started = 0; 
        spin_unlock_irqrestore(&np->lock, flags);

        /* Update the statistics. */
        update_rx_stats(np);
        update_tx_stats(np);

        /* Stop speed/duplex timers */
        del_timer(&np->speed_timer);
        del_timer(&np->duplex_timer);

        return 0;
}

static int
crisv32_eth_set_mac_address(struct net_device *dev, void *vpntr)
{
        int i;
        unsigned char *addr = ((struct sockaddr*)vpntr)->sa_data;
        
        reg_eth_rw_ma0_lo ma0_lo =
          { addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24)};
        
        reg_eth_rw_ma0_hi ma0_hi = { addr[4] | (addr[5] << 8) };

        struct crisv32_ethernet_local *np = netdev_priv(dev);

        /* Remember the address. */
        memcpy(dev->dev_addr, addr, dev->addr_len);

        /* 
         * Write the address to the hardware.
         * Note the way the address is wrapped:
         * ma0_l0 = a0_0 | (a0_1 << 8) | (a0_2 << 16) | (a0_3 << 24);
         * ma0_hi = a0_4 | (a0_5 << 8);
         */
        REG_WR(eth, np->eth_inst, rw_ma0_lo, ma0_lo);
        REG_WR(eth, np->eth_inst, rw_ma0_hi, ma0_hi);

        printk(KERN_INFO "%s: changed MAC to ", dev->name);

        for (i = 0; i < 5; i++)
                printk("%02X:", dev->dev_addr[i]);

        printk("%02X\n", dev->dev_addr[i]);

        return 0;
}

static irqreturn_t
crisv32rx_eth_interrupt(int irq, void *dev_id)
{
        struct net_device *dev = (struct net_device *) dev_id;
        struct crisv32_ethernet_local *np = netdev_priv(dev);
        reg_dma_r_masked_intr masked_in;

        masked_in = REG_RD(dma, np->dma_in_inst, r_masked_intr);
        
        if (masked_in.in_eop) {
                reg_dma_rw_ack_intr ack_intr = {0};     

                        /*
                 * Ack the rx irq even if we are not prepared to start
                 * polling. This is needed to handle incomming packets
                 * during the stop sequence.
                         */
                ack_intr.in_eop = 1;
                        REG_WR(dma, np->dma_in_inst, rw_ack_intr, ack_intr);
                if (netif_rx_schedule_prep(dev)) {
                        crisv32_disable_rx_ints(np);
                        /* put us onto the poll list */
                        __netif_rx_schedule(dev);
                }
        } else {
                /* Unexpected, ACK it and hope for the best.  */
                reg_dma_rw_ack_intr ack_intr = {0xffff};
                printk("unexpected eth-rx irq %x\n",
                       REG_RD_INT(dma, np->dma_in_inst, r_masked_intr));
                ack_intr.in_eop = 0;
                REG_WR(dma, np->dma_in_inst, rw_ack_intr, ack_intr);
        }

        return IRQ_HANDLED;
}

static irqreturn_t
crisv32tx_eth_interrupt(int irq, void *dev_id)
{
        reg_dma_rw_stat stat;
        dma_descr_data *dma_pos;
        reg_dma_rw_ack_intr ack_intr = { .data = 1 };
        reg_dma_r_masked_intr masked_out;
        
        struct net_device *dev = (struct net_device *) dev_id;
        struct crisv32_ethernet_local *np = netdev_priv(dev);
        unsigned long flags;
        
        masked_out = REG_RD(dma, np->dma_out_inst, r_masked_intr);
                
        /* Get the current output dma position. */
        stat = REG_RD(dma, np->dma_out_inst, rw_stat);
        if (stat.list_state == regk_dma_data_at_eol)
                dma_pos = &np->active_tx_desc->descr;
        else
                dma_pos = phys_to_virt(REG_RD_INT(dma, np->dma_out_inst,
                                                  rw_data));
        
        /* ack the interrupt, if it was active */
        if (masked_out.data)
        REG_WR(dma, np->dma_out_inst, rw_ack_intr, ack_intr);
        else
                printk("unexpected eth-tx irq %x\n", 
                       REG_RD_INT(dma, np->dma_out_inst, r_masked_intr));
        
        /* protect against ethernet excessive-col interrupts */
        spin_lock_irqsave(&np->lock, flags);

        /* Take care of transmited dma descriptors and report sent packet. */
        while (np->txpackets && ((&np->catch_tx_desc->descr != dma_pos)
                                 || netif_queue_stopped(dev))) {
                /* Update sent packet statistics. */
                np->stats.tx_bytes += np->catch_tx_desc->skb->len;
                np->stats.tx_packets++;
                
                dev_kfree_skb_irq(np->catch_tx_desc->skb);
                np->catch_tx_desc->skb = 0;
                np->txpackets--;
                np->catch_tx_desc =
                        phys_to_virt((int)np->catch_tx_desc->descr.next);
#ifdef CONFIG_CRIS_MACH_ARTPEC3
                if (np->gigabit_mode) {
                  np->intmem_tx_buf_catch->free = 1;
                  np->intmem_tx_buf_catch = np->intmem_tx_buf_catch->next;
                }
#endif
                netif_wake_queue(dev);
        }
        spin_unlock_irqrestore(&np->lock, flags);
        return IRQ_HANDLED;
}


/* Update receive errors. */
static void
update_rx_stats(struct crisv32_ethernet_local *np)
{
        reg_eth_rs_rec_cnt r;
        reg_eth_rs_phy_cnt rp;

        r = REG_RD(eth, np->eth_inst, rs_rec_cnt);
        rp = REG_RD(eth, np->eth_inst, rs_phy_cnt);

        np->stats.rx_fifo_errors += r.congestion;
        np->stats.rx_crc_errors += r.crc_err;
        np->stats.rx_frame_errors += r.align_err;
        np->stats.rx_length_errors += r.oversize;
}

/* Update transmit errors. */
static void
update_tx_stats(struct crisv32_ethernet_local *np)
{
        reg_eth_rs_tr_cnt r;

        r = REG_RD(eth, np->eth_inst, rs_tr_cnt);

        np->stats.collisions += r.single_col + r.mult_col;
        np->stats.tx_errors += r.deferred;
}

/* Get current statistics. */
static struct net_device_stats *
crisv32_get_stats(struct net_device *dev)
{
        unsigned long flags;
        struct crisv32_ethernet_local *np = netdev_priv(dev);
        
        spin_lock_irqsave(&np->lock, flags);

        update_rx_stats(np);
        update_tx_stats(np);

        spin_unlock_irqrestore(&np->lock, flags);

        return &np->stats;
}

/* Check for network errors. This acknowledge the received interrupt. */
static irqreturn_t
crisv32nw_eth_interrupt(int irq, void *dev_id)
{
        struct net_device *dev = (struct net_device *) dev_id;
        struct crisv32_ethernet_local *np = netdev_priv(dev);
        reg_eth_r_masked_intr intr_mask;
        int ack_intr = 0xffff;
        reg_eth_rw_clr_err clr_err;

        intr_mask = REG_RD(eth, np->eth_inst, r_masked_intr);

        /*
         * Check for underrun and/or excessive collisions. Note that the
         * rw_clr_err register clears both underrun and excessive collision
         * errors, so there's no need to check them separately.
         */
        if (np->sender_started
            && (intr_mask.urun || intr_mask.exc_col)) {
                unsigned long flags;
                dma_descr_data *dma_pos;
                reg_dma_rw_stat stat;

                /* Get the current output dma position. */
                stat = REG_RD(dma, np->dma_out_inst, rw_stat);
                if (stat.list_state == regk_dma_data_at_eol)
                        dma_pos = &np->active_tx_desc->descr;
                else
                        dma_pos = phys_to_virt(REG_RD_INT(dma,
                                                          np->dma_out_inst,
                                                          rw_data));

                /*
                 * Protect against the tx-interrupt messing with
                 * the tx-ring.
                 */
                spin_lock_irqsave(&np->lock, flags);
                /*
                 * If we have more than one packet in the tx-ring
                 * drop one and move ahead. Upper layers rely on
                 * packeloss when doing congestion control.
                 */
                if (intr_mask.exc_col && np->txpackets > 1) {
                        dev_kfree_skb_irq(np->catch_tx_desc->skb);
                        np->catch_tx_desc->skb = 0;
                        np->catch_tx_desc = 
                                phys_to_virt((int)
                                             np->catch_tx_desc->descr.next);
                        np->txpackets--;
                        netif_wake_queue(dev);
                }
                np->ctxt_out.next = 0;
                if (np->txpackets) {
                        np->ctxt_out.saved_data = (void *)
                                virt_to_phys(&np->catch_tx_desc->descr);
                        np->ctxt_out.saved_data_buf =
                                np->catch_tx_desc->descr.buf;
                        
                        /* restart the DMA */
                        DMA_START_CONTEXT(np->dma_out_inst,
                                          (int) virt_to_phys(&np->ctxt_out));
                }
                else {
                        /* let the next packet restart the DMA */
                        np->ctxt_out.saved_data = (void *)
                                virt_to_phys(&np->active_tx_desc->descr);
                        np->sender_started = 0;
                }
                
                spin_unlock_irqrestore(&np->lock, flags);
                np->stats.tx_errors++;
        }

        REG_WR_INT(eth, np->eth_inst, rw_ack_intr, ack_intr);
        clr_err.clr = 1;
        REG_WR(eth, np->eth_inst, rw_clr_err, clr_err);
        
        update_rx_stats(np);
        update_tx_stats(np);
        
        return IRQ_HANDLED;
}

/* We have a good packet(s), get it/them out of the buffers. */
static void
crisv32_eth_receive_packet(struct net_device *dev)
{
        int length;
        struct sk_buff *skb;
        struct crisv32_ethernet_local *np = netdev_priv(dev);
        struct sk_buff *tmp;
        unsigned long flags;

        DEBUG(printk("crisv32_receive_packet\n"));

        /* Activate LED */
        spin_lock_irqsave(&np->leds->led_lock, flags);
        if (!np->leds->led_active && time_after(jiffies, 
                                                np->leds->led_next_time)) {
                /* light the network leds depending on the current speed. */
                crisv32_set_network_leds(LED_ACTIVITY, dev);

                /* Set the earliest time we may clear the LED */
                np->leds->led_next_time = jiffies + NET_FLASH_TIME;
                np->leds->led_active = 1;
                np->leds->clear_led_timer.data = (unsigned long) dev;
                mod_timer(&np->leds->clear_led_timer, jiffies + HZ/10);
        }
        spin_unlock_irqrestore(&np->leds->led_lock, flags);

        /* Discard CRC (4 bytes). */
        length = (np->active_rx_desc->descr.after) - 
                (np->active_rx_desc->descr.buf) - 4;

        /* Update received packet statistics. */
        np->stats.rx_bytes += length;

        if (np->active_rx_desc != np->last_rx_desc) {
#ifdef CONFIG_CRIS_MACH_ARTPEC3
                if (np->gigabit_mode) {
                        skb = dev_alloc_skb(length);
                        if(!skb) {
                                np->stats.rx_errors++;
                                printk(KERN_NOTICE "%s: memory squeeze,"
                                       " dropping packet.", dev->name);
                                return;
                        }
                        /* Allocate room for the packet body. */
                        skb_put(skb, length - ETHER_HEAD_LEN);
                        /* Allocate room for the header and copy the data to
                         * the SKB */
                        memcpy(skb_push(skb, ETHER_HEAD_LEN),
                               crisv32_intmem_phys_to_virt((unsigned long)np->active_rx_desc->descr.buf), length);
                        skb->dev = dev;
                        skb->protocol = eth_type_trans(skb, dev);
                        skb->ip_summed = CHECKSUM_NONE;
                        /* Send the packet to the upper layer. */
                        netif_receive_skb(skb);
                        np->last_rx_desc =
                                (void *) phys_to_virt(np->last_rx_desc->descr.next);
                        np->newbuf = 0;
                } else {
#endif
                        tmp = dev_alloc_skb(MAX_MEDIA_DATA_SIZE);
                        if (!tmp) {
                                np->stats.rx_errors++;
                                printk(KERN_NOTICE "%s: memory squeeze,"
                                       " dropping packet.",
                                       dev->name);
                                return;
                        }
                        skb = np->active_rx_desc->skb;
                        np->active_rx_desc->skb = tmp;
                        skb_put(skb, length);

                        np->newbuf = 
                                virt_to_phys(np->active_rx_desc->skb->data);

                        skb->dev = dev;
                        skb->protocol = eth_type_trans(skb, dev);
                        skb->ip_summed = CHECKSUM_NONE;

                        /* Send the packet to the upper layer. */
                        netif_receive_skb(skb);
                        np->last_rx_desc =
                                phys_to_virt((int)
                                             np->last_rx_desc->descr.next);
                }
#ifdef CONFIG_CRIS_MACH_ARTPEC3
        }
#endif

        /* Forward rotate the receive ring.  */
        crisv32_eth_rx_ring_advance(np);
}

/*
 * Is there work to do in the rx-path?
 */
static inline int crisv32_has_rx_work(struct crisv32_ethernet_local *np,
                                      dma_descr_data *active)
{
        int mw;
        mw = (active->in_eop == 1 && np->new_rx_package);
        return mw;
}

/*
 * NAPI poll
 *
 * We are allowed to poll dev->quota skb's from the rx-ring.
 * Must update *budget and dev->quota. If we are done, remove us from the
 * poll list and re-enable interrupts.
 *
 * TODO: Add tx-reclaim,
 *       Are there races when we re-enable ints?
 */
static int crisv32_eth_poll(struct net_device *dev, int *budget)
{
        struct crisv32_ethernet_local *np = netdev_priv(dev);
        int workdone = dev->quota;
        int morework;
        reg_dma_rw_ack_intr ack_intr = {0};     

        ack_intr.in_eop = 1;

        if (np->new_rx_package == 0) {
        /*
                 * In the previous round we pulled a packet from the ring but 
                 * we didn't advance the ring due to hw DMA bug. Try to do it
                 * now.
         */
                np->new_rx_package = 1;
                crisv32_eth_rx_ring_advance(np);
        }

        morework = crisv32_has_rx_work(np, &np->active_rx_desc->descr);

        while (morework && dev->quota)
        {
                crisv32_eth_receive_packet(dev);
                dev->quota--;
                np->stats.rx_packets++;

                /* Ack irq and restart rx dma */
                REG_WR(dma, np->dma_in_inst, rw_ack_intr, ack_intr);
                DMA_CONTINUE_DATA(np->dma_in_inst);

                morework = crisv32_has_rx_work(np, &np->active_rx_desc->descr);
        }
        update_rx_stats(np);

        /* it's our responsability to update the global budget. */
        *budget -= (workdone - dev->quota);

        if (!morework) {                
                /* first mark as done, then enable irq's */
                netif_rx_complete(dev);
                crisv32_enable_rx_ints(np);
        }

        return morework;
}

/* 
 * This function (i.e. hard_start_xmit) is protected from concurent calls by a
 * spinlock (xmit_lock) in the net_device structure.
 */
static int
crisv32_eth_send_packet(struct sk_buff *skb, struct net_device *dev)
{
        struct crisv32_ethernet_local *np = netdev_priv(dev);
        unsigned char *buf = skb->data;
        unsigned long flags;

        dev->trans_start = jiffies;
        
        spin_lock_irqsave(&np->leds->led_lock, flags);
        if (!np->leds->led_active && time_after(jiffies, 
                                                np->leds->led_next_time)) {
                /* light the network leds depending on the current speed. */
                crisv32_set_network_leds(LED_ACTIVITY, dev);

                /* Set the earliest time we may clear the LED */
                np->leds->led_next_time = jiffies + NET_FLASH_TIME;
                np->leds->led_active = 1;
                np->leds->clear_led_timer.data = (unsigned long) dev;
                mod_timer(&np->leds->clear_led_timer, jiffies + HZ/10);
        }
        spin_unlock_irqrestore(&np->leds->led_lock, flags);

        /*
         * Need to disable irq to avoid updating pointer in interrupt while
         * sending packets.
         */
        spin_lock_irqsave(&np->lock, flags);
        
        np->active_tx_desc->skb = skb;
#ifdef CONFIG_CRIS_MACH_ARTPEC3
        if (np->gigabit_mode) {
                if(np->intmem_tx_buf_active->free) {
                        memcpy(np->intmem_tx_buf_active->buf,
                               skb->data, skb->len);
                        np->intmem_tx_buf_active->free = 0;
                        crisv32_eth_hw_send_packet(
                                np->intmem_tx_buf_active->buf, skb->len, np);
                        np->intmem_tx_buf_active =
                                np->intmem_tx_buf_active->next;
                } else {
                        printk("%s: Internal tx memory buffer not free!\n\r",
                               __FILE__);
                        spin_unlock_irqrestore(&np->lock, flags);
                        return 1;
                }
        }
        else 
#endif
        {
                crisv32_eth_hw_send_packet(buf, skb->len, np);
        }

        /* Stop queue if full. */
        if (
#ifdef CONFIG_CRIS_MACH_ARTPEC3
                phys_to_virt((int)np->active_tx_desc->descr.next)
#else
                np->active_tx_desc
#endif
                == np->catch_tx_desc) {
                netif_stop_queue(dev);
        }
        
        np->txpackets++;
        spin_unlock_irqrestore(&np->lock, flags);
        
        return 0;
}


static void
crisv32_eth_hw_send_packet(unsigned char *buf, int length, void *priv)
{
        struct crisv32_ethernet_local *np =
                (struct crisv32_ethernet_local *) priv;

        /* Configure the tx dma descriptor. */
#ifdef CONFIG_CRIS_MACH_ARTPEC3
        if (np->gigabit_mode) {
          np->active_tx_desc->descr.buf = 
                  (unsigned char *) crisv32_intmem_virt_to_phys(buf);
        } else 
#endif
        {
          np->active_tx_desc->descr.buf = (unsigned char *) virt_to_phys(buf);
        }
          
        np->active_tx_desc->descr.after = np->active_tx_desc->descr.buf +
                length;
        np->active_tx_desc->descr.intr = 1;        
        np->active_tx_desc->descr.out_eop = 1;

        /* Move eol. */
        np->active_tx_desc->descr.eol = 1;
        np->prev_tx_desc->descr.eol = 0;


        /* Update pointers. */
        np->prev_tx_desc = np->active_tx_desc;
        np->active_tx_desc = phys_to_virt((int)np->active_tx_desc->descr.next);

        /* Start DMA. */
        crisv32_start_dma_out(np);
}

static void
crisv32_start_dma_out(struct crisv32_ethernet_local* np)
{
        if (!np->sender_started) {
                /* Start DMA for the first time. */
                np->ctxt_out.saved_data_buf = np->prev_tx_desc->descr.buf;
                REG_WR(dma, np->dma_out_inst, rw_group_down,
                       (int) virt_to_phys(&np->ctxt_out));
                DMA_WR_CMD(np->dma_out_inst, regk_dma_load_c);
                DMA_WR_CMD(np->dma_out_inst, regk_dma_load_d | regk_dma_burst);
                np->sender_started = 1;
        } else {
                DMA_CONTINUE_DATA(np->dma_out_inst);
        }
}

/* 
 * Called by upper layers if they decide it took too long to complete sending
 * a packet - we need to reset and stuff.
 */
static void
crisv32_eth_tx_timeout(struct net_device *dev)
{
        struct crisv32_ethernet_local *np = netdev_priv(dev);
        reg_dma_rw_stat stat = {0};
        unsigned long flags;

        printk(KERN_WARNING "%s: transmit timed out\n", dev->name);

        spin_lock_irqsave(&np->lock, flags);
        update_tx_stats(np);

        crisv32_ethernet_bug(dev);

        np->txpackets = 0;
        /* Update error stats. */
        np->stats.tx_errors++; 

        /* Reset the TX DMA in case it has hung on something. */
        DMA_RESET(np->dma_out_inst);
        do {
                stat = REG_RD(dma, np->dma_out_inst, rw_stat);
        } while (stat.mode != regk_dma_rst);

        /* Reset the tranceiver. */
        crisv32_eth_reset_tranceiver(dev);

        /* Get rid of the packets that never got an interrupt. */
        do {
                if (np->catch_tx_desc->skb)
                        dev_kfree_skb(np->catch_tx_desc->skb);
                
                np->catch_tx_desc->skb = 0;
                np->catch_tx_desc =
                        phys_to_virt((int)np->catch_tx_desc->descr.next);
        } while (np->catch_tx_desc != np->active_tx_desc);

        reg_eth_rw_gen_ctrl gen_ctrl = { 0 };
        gen_ctrl.en = regk_eth_yes;
        REG_WR(eth, np->eth_inst, rw_gen_ctrl, gen_ctrl);

        int ack_intr = 0xffff;
        REG_WR_INT(eth, np->eth_inst, rw_ack_intr, ack_intr);
        reg_eth_rw_clr_err clr_err;
        clr_err.clr = 1;
        REG_WR(eth, np->eth_inst, rw_clr_err, clr_err);

        crisv32_enable_tx_ints(np);

        DMA_ENABLE(np->dma_out_inst);
#ifdef CONFIG_CRIS_MACH_ARTPEC3
        DMA_WR_CMD(np->dma_out_inst, regk_dma_set_w_size4);
#endif

        /* Next packet will restart output DMA. */
        np->sender_started = 0;

        spin_unlock_irqrestore(&np->lock, flags);

        /* Tell the upper layers we're ok again. */
        netif_wake_queue(dev);
}

/*
 * Set or clear the multicast filter for this adaptor.
 * num_addrs == -1      Promiscuous mode, receive all packets
 * num_addrs == 0       Normal mode, clear multicast list
 * num_addrs > 0        Multicast mode, receive normal and MC packets,
 *                      and do best-effort filtering.
 */
static void
crisv32_eth_set_multicast_list(struct net_device *dev)
{
        int num_addr = dev->mc_count;
        unsigned long int lo_bits;
        unsigned long int hi_bits;
        reg_eth_rw_rec_ctrl rec_ctrl = {0};
        reg_eth_rw_ga_lo ga_lo = {0};
        reg_eth_rw_ga_hi ga_hi = {0};
        struct crisv32_ethernet_local *np = netdev_priv(dev);

        if (dev->flags & IFF_PROMISC) {
                /* Promiscuous mode. */
                lo_bits = 0xfffffffful;
                hi_bits = 0xfffffffful;

                /* Enable individual receive. */
                rec_ctrl = (reg_eth_rw_rec_ctrl) REG_RD(eth, np->eth_inst,
                                                        rw_rec_ctrl);
                rec_ctrl.individual = regk_eth_yes;
                REG_WR(eth, np->eth_inst, rw_rec_ctrl, rec_ctrl);
        } else if (dev->flags & IFF_ALLMULTI) {
                /* Enable all multicasts. */
                lo_bits = 0xfffffffful;
                hi_bits = 0xfffffffful;

                /* Disable individual receive */
                rec_ctrl =
                  (reg_eth_rw_rec_ctrl) REG_RD(eth, np->eth_inst, rw_rec_ctrl);
                rec_ctrl.individual = regk_eth_no;
                REG_WR(eth, np->eth_inst, rw_rec_ctrl, rec_ctrl);
        } else if (num_addr == 0) {
                /* Normal, clear the mc list. */
                lo_bits = 0x00000000ul;
                hi_bits = 0x00000000ul;

                /* Disable individual receive */
                rec_ctrl =
                  (reg_eth_rw_rec_ctrl) REG_RD(eth, np->eth_inst, rw_rec_ctrl);
                rec_ctrl.individual = regk_eth_no;
                REG_WR(eth, np->eth_inst, rw_rec_ctrl, rec_ctrl);
        } else {
                /* MC mode, receive normal and MC packets. */
                char hash_ix;
                struct dev_mc_list *dmi = dev->mc_list;
                int i;
                char *baddr;
                lo_bits = 0x00000000ul;
                hi_bits = 0x00000000ul;
                
                for (i = 0; i < num_addr; i++) {
                        /* Calculate the hash index for the GA registers. */
                        hash_ix = 0;
                        baddr = dmi->dmi_addr;
                        hash_ix ^= (*baddr) & 0x3f;
                        hash_ix ^= ((*baddr) >> 6) & 0x03;
                        ++baddr;
                        hash_ix ^= ((*baddr) << 2) & 0x03c;
                        hash_ix ^= ((*baddr) >> 4) & 0xf;
                        ++baddr;
                        hash_ix ^= ((*baddr) << 4) & 0x30;
                        hash_ix ^= ((*baddr) >> 2) & 0x3f;
                        ++baddr;
                        hash_ix ^= (*baddr) & 0x3f;
                        hash_ix ^= ((*baddr) >> 6) & 0x03;
                        ++baddr;
                        hash_ix ^= ((*baddr) << 2) & 0x03c;
                        hash_ix ^= ((*baddr) >> 4) & 0xf;
                        ++baddr;
                        hash_ix ^= ((*baddr) << 4) & 0x30;
                        hash_ix ^= ((*baddr) >> 2) & 0x3f;

                        hash_ix &= 0x3f;

                        if (hash_ix > 32)
                                hi_bits |= (1 << (hash_ix - 32));
                        else
                                lo_bits |= (1 << hash_ix);

                        dmi = dmi->next;
                }
                
                /* Disable individual receive. */
                rec_ctrl =
                  (reg_eth_rw_rec_ctrl) REG_RD(eth, np->eth_inst, rw_rec_ctrl);
                rec_ctrl.individual = regk_eth_no;
                REG_WR(eth, np->eth_inst, rw_rec_ctrl, rec_ctrl);
        }

        ga_lo.tbl = (unsigned int) lo_bits;
        ga_hi.tbl = (unsigned int) hi_bits;

        REG_WR(eth, np->eth_inst, rw_ga_lo, ga_lo);
        REG_WR(eth, np->eth_inst, rw_ga_hi, ga_hi);
}

static int
crisv32_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
        struct mii_ioctl_data *data = if_mii(ifr);
        struct crisv32_ethernet_local *np = netdev_priv(dev);
        int old_autoneg;

        spin_lock(&np->lock); /* Preempt protection */
        switch (cmd) {
                case SIOCGMIIPHY: /* Get PHY address */
                        data->phy_id = np->mdio_phy_addr;
                        break;
                case SIOCGMIIREG: /* Read MII register */
                        data->val_out = crisv32_eth_get_mdio_reg(dev,
                                                                 data->reg_num);
                        break;
                case SIOCSMIIREG: /* Write MII register */
                        crisv32_eth_set_mdio_reg(dev, data->reg_num,
                                                 data->val_in);
                        break;
                case SET_ETH_ENABLE_LEDS:
                        use_network_leds = 1;
                        break;
                case SET_ETH_DISABLE_LEDS:
                        use_network_leds = 0;
                        break;
                case SET_ETH_AUTONEG:
                        old_autoneg = autoneg_normal;
                        autoneg_normal = *(int*)data;
                        if (autoneg_normal != old_autoneg)
                                crisv32_eth_negotiate(dev);
                        break;
        default:
                spin_unlock(&np->lock); /* Preempt protection */
                return -EINVAL;
        }
        spin_unlock(&np->lock);
        return 0;
}

static int crisv32_eth_get_settings(struct net_device *dev,
                             struct ethtool_cmd *ecmd)
{
        struct crisv32_ethernet_local *np = netdev_priv(dev);
        /* What about GMII and 1000xpause? not included in ethtool.h */
        ecmd->supported = SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII |
                          SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
                          SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full;
#ifdef CONFIG_CRIS_MACH_ARTPEC3
        ecmd->supported |= SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full;
#endif
        ecmd->port = PORT_TP;
        ecmd->transceiver = XCVR_EXTERNAL;
        ecmd->phy_address = np->mdio_phy_addr;
        ecmd->speed = np->current_speed;
        ecmd->duplex = np->full_duplex;
        ecmd->advertising = ADVERTISED_TP;

        if (np->current_duplex == autoneg && np->current_speed_selection == 0)
                ecmd->advertising |= ADVERTISED_Autoneg;
        else {
                ecmd->advertising |=
                        ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
                        ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
#ifdef CONFIG_CRIS_MACH_ARTPEC3
                ecmd->advertising |= ADVERTISED_1000baseT_Half |
                        ADVERTISED_1000baseT_Full;
#endif
                if (np->current_speed_selection == 10)
                        ecmd->advertising &= ~(ADVERTISED_100baseT_Half |
                                               ADVERTISED_100baseT_Full |
                                               ADVERTISED_1000baseT_Half |
                                               ADVERTISED_1000baseT_Full);

                else if (np->current_speed_selection == 100)
                        ecmd->advertising &= ~(ADVERTISED_10baseT_Half |
                                               ADVERTISED_10baseT_Full |
                                               ADVERTISED_1000baseT_Half |
                                               ADVERTISED_1000baseT_Full);

                else if (np->current_speed_selection == 1000)
                        ecmd->advertising &= ~(ADVERTISED_10baseT_Half |
                                               ADVERTISED_10baseT_Full |
                                               ADVERTISED_100baseT_Half |
                                               ADVERTISED_100baseT_Full);

                if (np->current_duplex == half)
                        ecmd->advertising &= ~(ADVERTISED_10baseT_Full |
                                               ADVERTISED_100baseT_Full |
                                               ADVERTISED_1000baseT_Full);
                else if (np->current_duplex == full)
                        ecmd->advertising &= ~(ADVERTISED_10baseT_Half |
                                               ADVERTISED_100baseT_Half |
                                               ADVERTISED_1000baseT_Half);
        }

        ecmd->autoneg = AUTONEG_ENABLE;
        return 0;
}

static int crisv32_eth_set_settings(struct net_device *dev,
                             struct ethtool_cmd *ecmd)
{
        if (ecmd->autoneg == AUTONEG_ENABLE) {
                crisv32_eth_set_duplex(dev, autoneg);
                crisv32_eth_set_speed(dev, 0);
        } else {
                crisv32_eth_set_duplex(dev, ecmd->duplex);
                crisv32_eth_set_speed(dev, ecmd->speed);
        }

        return 0;
}

static void crisv32_eth_get_drvinfo(struct net_device *dev,
                             struct ethtool_drvinfo *info)
{
        strncpy(info->driver, "ETRAX FS", sizeof(info->driver) - 1);
        strncpy(info->version, "$Revision: 1.1.1.1 $", sizeof(info->version) - 1);
        strncpy(info->fw_version, "N/A", sizeof(info->fw_version) - 1);
        strncpy(info->bus_info, "N/A", sizeof(info->bus_info) - 1);
}

static int crisv32_eth_nway_reset(struct net_device *dev)
{
        struct crisv32_ethernet_local *np = netdev_priv(dev);

        if (np->current_duplex == autoneg && np->current_speed_selection == 0)
                crisv32_eth_negotiate(dev);
        return 0;
}

static struct ethtool_ops crisv32_ethtool_ops = {
        .get_settings   = crisv32_eth_get_settings,
        .set_settings   = crisv32_eth_set_settings,
        .get_drvinfo    = crisv32_eth_get_drvinfo,
        .nway_reset     = crisv32_eth_nway_reset,
        .get_link       = ethtool_op_get_link,
};

/* Is this function really needed? Use ethtool instead? */
static int
crisv32_eth_set_config(struct net_device *dev, struct ifmap *map)
{
        struct crisv32_ethernet_local *np = netdev_priv(dev);

        spin_lock(&np->lock); /* Preempt protection */

        switch(map->port) {
                case IF_PORT_UNKNOWN:
                        /* Use autoneg */
                        crisv32_eth_set_speed(dev, 0);
                        crisv32_eth_set_duplex(dev, autoneg);
                        break;
                case IF_PORT_10BASET:
                        crisv32_eth_set_speed(dev, 10);
                        crisv32_eth_set_duplex(dev, autoneg);
                        break;
                case IF_PORT_100BASET:
                case IF_PORT_100BASETX:
                        crisv32_eth_set_speed(dev, 100);
                        crisv32_eth_set_duplex(dev, autoneg);
                        break;
                case IF_PORT_100BASEFX:
                case IF_PORT_10BASE2:
                case IF_PORT_AUI:
                        spin_unlock(&np->lock);
                        return -EOPNOTSUPP;
                        break;
                default:
                        printk(KERN_ERR "%s: Invalid media selected",
                               dev->name);
                        spin_unlock(&np->lock);
                        return -EINVAL;
        }
        spin_unlock(&np->lock);
        return 0;
}

#ifdef CONFIG_CRIS_MACH_ARTPEC3
/* 
 * Switch the behaviour of the tx and rx buffers using 
 * external or internal memory. Usage of the internal 
 * memory is required for gigabit operation.
 */
static void 
crisv32_eth_switch_intmem_usage(struct net_device *dev) 
{
        struct crisv32_ethernet_local *np = netdev_priv(dev);

        int i;
        reg_dma_rw_stat stat;
        reg_dma_rw_cfg cfg = {0};
        reg_dma_rw_intr_mask intr_mask_in = { .in_eop = regk_dma_yes };
        reg_dma_rw_ack_intr ack_intr = { .data = 1,.in_eop = 1 };
        unsigned char *intmem_tmp;

        /* Notify the kernel that the interface has stopped */
        netif_stop_queue(dev);

        /* Stop the receiver DMA */
        cfg.en = regk_dma_no;
        REG_WR(dma, np->dma_in_inst, rw_cfg, cfg);

        if (!(np->gigabit_mode)) {
                /* deallocate SKBs in rx_desc */
                for (i = 0; i < NBR_RX_DESC; i++)
                        dev_kfree_skb(np->dma_rx_descr_list[i].skb);

                /* Init TX*/
                for(i=0; i < NBR_INTMEM_TX_BUF; i++) {
                        /* Allocate internal memory */
                        intmem_tmp = NULL;
                        intmem_tmp = crisv32_intmem_alloc(MAX_MEDIA_DATA_SIZE,
                                                          32);
                        /* Check that we really got the memory */
                        if (intmem_tmp == NULL) {
                                printk(KERN_ERR "%s: Can't allocate intmem for"
                                       " RX buffer nbr: %d\n", dev->name, i);
                                return;
                        }
                        /* Setup the list entry */
                        np->tx_intmem_buf_list[i].free = 1;
                        np->tx_intmem_buf_list[i].buf = intmem_tmp;
                        np->tx_intmem_buf_list[i].next = 
                                &np->tx_intmem_buf_list[i + 1];
                }
                /* Setup the last list entry */
                np->tx_intmem_buf_list[NBR_INTMEM_TX_BUF - 1].next = 
                        &np->tx_intmem_buf_list[0];
                /* Setup initial pointer */
                np->intmem_tx_buf_active = np->tx_intmem_buf_list;
                np->intmem_tx_buf_catch = np->tx_intmem_buf_list;

                /* Init RX */
                for (i=0; i < NBR_INTMEM_RX_DESC; i++) {
                        /* Allocate internal memory */
                        intmem_tmp = NULL;
                        intmem_tmp = crisv32_intmem_alloc(MAX_MEDIA_DATA_SIZE, 
                                                          32);
                        /* Check that we really got the memory */
                        if (intmem_tmp == NULL) {
                                printk(KERN_ERR "%s: Can't allocate intmem for"
                                       " desc nbr: %d\n", dev->name, i);
                                return;
                        }
                        /* Setup the descriptors*/
                        np->dma_rx_descr_list[i].skb = NULL;
                        np->dma_rx_descr_list[i].descr.buf = 
                             (void *) crisv32_intmem_virt_to_phys(intmem_tmp);
                        np->dma_rx_descr_list[i].descr.after =
                             (void *) crisv32_intmem_virt_to_phys(intmem_tmp + MAX_MEDIA_DATA_SIZE);
                        np->dma_rx_descr_list[i].descr.eol = 0;
                        np->dma_rx_descr_list[i].descr.in_eop = 0;
                        np->dma_rx_descr_list[i].descr.next =
                             (void *) virt_to_phys(&np->dma_rx_descr_list[i+1].descr);
                }
                /* Setup the last rx descriptor */
                np->dma_rx_descr_list[NBR_INTMEM_RX_DESC - 1].descr.eol = 1;
                np->dma_rx_descr_list[NBR_INTMEM_RX_DESC - 1].descr.next =
                   (void*) virt_to_phys(&np->dma_rx_descr_list[0].descr);
                /* Initialise initial receive pointers. */
                np->active_rx_desc = &np->dma_rx_descr_list[0];
                np->prev_rx_desc = 
                        &np->dma_rx_descr_list[NBR_INTMEM_RX_DESC - 1];
                np->last_rx_desc = np->prev_rx_desc;

                np->gigabit_mode = 1;
        } else {
                /* dealloc TX intmem */
                for(i=0; i < NBR_INTMEM_TX_BUF; i++)
                        crisv32_intmem_free(np->tx_intmem_buf_list[i].buf);

                /* dealloc RX intmem */
                for (i=0; i < NBR_INTMEM_RX_DESC; i++)
                        crisv32_intmem_free(crisv32_intmem_phys_to_virt((unsigned long)np->dma_rx_descr_list[i].descr.buf));

                /* Setup new rx_desc and alloc SKBs */
                for (i = 0; i < NBR_RX_DESC; i++) {
                        struct sk_buff *skb;
                        
                        skb = dev_alloc_skb(MAX_MEDIA_DATA_SIZE);
                        np->dma_rx_descr_list[i].skb = skb;
                        np->dma_rx_descr_list[i].descr.buf =
                                (char*)virt_to_phys(skb->data);
                        np->dma_rx_descr_list[i].descr.after =
                           (char*)virt_to_phys(skb->data + MAX_MEDIA_DATA_SIZE);

                        np->dma_rx_descr_list[i].descr.eol = 0;
                        np->dma_rx_descr_list[i].descr.in_eop = 0;
                        np->dma_rx_descr_list[i].descr.next =
                           (void *) virt_to_phys(&np->dma_rx_descr_list[i + 1].descr);
                }
    
                np->dma_rx_descr_list[NBR_RX_DESC - 1].descr.eol = 1;
                np->dma_rx_descr_list[NBR_RX_DESC - 1].descr.next =
                   (void *) virt_to_phys(&np->dma_rx_descr_list[0].descr);
      
                /* Initialise initial receive pointers. */
                np->active_rx_desc = &np->dma_rx_descr_list[0];
                np->prev_rx_desc = &np->dma_rx_descr_list[NBR_RX_DESC - 1];
                np->last_rx_desc = np->prev_rx_desc;

                np->gigabit_mode = 0;
        }

        /* Fill context descriptors. */
        np->ctxt_in.next = 0;        
        np->ctxt_in.saved_data =
           (dma_descr_data *) virt_to_phys(&np->dma_rx_descr_list[0].descr);
        np->ctxt_in.saved_data_buf = np->dma_rx_descr_list[0].descr.buf;

        /* Enable irq and make sure that the irqs are cleared. */
        REG_WR(dma, np->dma_in_inst, rw_intr_mask, intr_mask_in);
        REG_WR(dma, np->dma_in_inst, rw_ack_intr, ack_intr);

        /* Start input dma */
        cfg.en = regk_dma_yes;
        REG_WR(dma, np->dma_in_inst, rw_cfg, cfg);
        REG_WR(dma, np->dma_in_inst, rw_group_down,
               (int) virt_to_phys(&np->ctxt_in));

        DMA_WR_CMD(np->dma_in_inst, regk_dma_load_c);
        DMA_WR_CMD(np->dma_in_inst, regk_dma_load_d | regk_dma_burst);
#ifdef CONFIG_CRIS_MACH_ARTPEC3
  /* Reset the dma word size. */
        DMA_WR_CMD(np->dma_in_inst, regk_dma_set_w_size2);
#endif

        netif_wake_queue(dev);

        stat = REG_RD(dma, np->dma_in_inst, rw_stat);
}
#endif

static void
crisv32_eth_negotiate(struct net_device *dev)
{
        unsigned short data =
            crisv32_eth_get_mdio_reg(dev, MII_ADVERTISE);
        unsigned short ctrl1000 =
            crisv32_eth_get_mdio_reg(dev, MII_CTRL1000);
        struct crisv32_ethernet_local *np = netdev_priv(dev);

        /* Make all capabilities available */
        data |= ADVERTISE_10HALF | ADVERTISE_10FULL |
                ADVERTISE_100HALF | ADVERTISE_100FULL;
        ctrl1000 |= ADVERTISE_1000HALF | ADVERTISE_1000FULL;

        /* Remove the speed capabilities that we that do not want */
        switch (np->current_speed_selection) {
                case 10 :
                        data &= ~(ADVERTISE_100HALF | ADVERTISE_100FULL);
                        ctrl1000 &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
                        break;
                case 100 :
                        data &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL);
                        ctrl1000 &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
                        break;
                case 1000 :
                        data &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
                                  ADVERTISE_100HALF | ADVERTISE_100FULL);
                        break;
        }

        /* Remove the duplex capabilites that we do not want */
        if (np->current_duplex == full) {
                data &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
                ctrl1000 &= ~(ADVERTISE_1000HALF);
        }
        else if (np->current_duplex == half) {
                data &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
                ctrl1000 &= ~(ADVERTISE_1000FULL);
        }

        crisv32_eth_set_mdio_reg(dev, MII_ADVERTISE, data);
#ifdef CONFIG_CRIS_MACH_ARTPEC3
        crisv32_eth_set_mdio_reg(dev, MII_CTRL1000, ctrl1000);
#endif

        /* Renegotiate with link partner */
        if (autoneg_normal) {
          data = crisv32_eth_get_mdio_reg(dev, MII_BMCR);
          data |= BMCR_ANENABLE | BMCR_ANRESTART;
        }
        crisv32_eth_set_mdio_reg(dev, MII_BMCR, data);
}
static void
crisv32_eth_check_speed(unsigned long idev)
{
        static int led_initiated = 0;
        struct net_device *dev = (struct net_device *) idev;
        struct crisv32_ethernet_local *np = netdev_priv(dev);

        unsigned long data;
        int old_speed;
        unsigned long flags;
        
        BUG_ON(!np);
        BUG_ON(!np->transceiver);

        spin_lock(&np->transceiver_lock);

        old_speed = np->current_speed;
        data = crisv32_eth_get_mdio_reg(dev, MII_BMSR);

        if (!(data & BMSR_LSTATUS))
                np->current_speed = 0;
        else
                np->transceiver->check_speed(dev);

#ifdef CONFIG_CRIS_MACH_ARTPEC3
        if ((old_speed != np->current_speed)
            && ((old_speed == 1000) || (np->current_speed == 1000))) {
                /* Switch between mii and gmii */
                reg_eth_rw_gen_ctrl gen_ctrl = REG_RD(eth, np->eth_inst,
                                                      rw_gen_ctrl);
                reg_eth_rw_tr_ctrl tr_ctrl = REG_RD(eth, np->eth_inst,
                                                    rw_tr_ctrl);
                if (old_speed == 1000) {
                        gen_ctrl.phy = regk_eth_mii;
                        gen_ctrl.gtxclk_out = regk_eth_no;
                        tr_ctrl.carrier_ext = regk_eth_no;
                }
                else {
                        gen_ctrl.phy = regk_eth_gmii;
                        gen_ctrl.gtxclk_out = regk_eth_yes;
                        tr_ctrl.carrier_ext = regk_eth_yes;
                }
                REG_WR(eth, np->eth_inst, rw_tr_ctrl, tr_ctrl);
                REG_WR(eth, np->eth_inst, rw_gen_ctrl, gen_ctrl);

                crisv32_eth_switch_intmem_usage(dev);
        }
#endif

        spin_lock_irqsave(&np->leds->led_lock, flags);
        if ((old_speed != np->current_speed) || !led_initiated) {
                led_initiated = 1;
                np->leds->clear_led_timer.data = (unsigned long) dev;
                if (np->current_speed) {
                        netif_carrier_on(dev);
                        crisv32_set_network_leds(LED_LINK, dev);
                } else {
                        netif_carrier_off(dev);
                        crisv32_set_network_leds(LED_NOLINK, dev);
                }
        }
        spin_unlock_irqrestore(&np->leds->led_lock, flags);

        /* Reinitialize the timer. */
        np->speed_timer.expires = jiffies + NET_LINK_UP_CHECK_INTERVAL;
        add_timer(&np->speed_timer);

        spin_unlock(&np->transceiver_lock);
}

static void
crisv32_eth_set_speed(struct net_device *dev, unsigned long speed)
{
        struct crisv32_ethernet_local *np = netdev_priv(dev);
        
        spin_lock(&np->transceiver_lock);
        if (np->current_speed_selection != speed) {
                np->current_speed_selection = speed;
                crisv32_eth_negotiate(dev);
        }
        spin_unlock(&np->transceiver_lock);
}

static void
crisv32_eth_check_duplex(unsigned long idev)
{
        struct net_device *dev = (struct net_device *) idev;
        struct crisv32_ethernet_local *np = netdev_priv(dev);
        reg_eth_rw_rec_ctrl rec_ctrl;
        int old_duplex = np->full_duplex;

        np->transceiver->check_duplex(dev);
        
        if (old_duplex != np->full_duplex) {
                /* Duplex changed. */
                rec_ctrl = (reg_eth_rw_rec_ctrl) REG_RD(eth, np->eth_inst,
                                                        rw_rec_ctrl);
                rec_ctrl.duplex = np->full_duplex;
                REG_WR(eth, np->eth_inst, rw_rec_ctrl, rec_ctrl);
        }

        /* Reinitialize the timer. */
        np->duplex_timer.expires = jiffies + NET_DUPLEX_CHECK_INTERVAL;
        add_timer(&np->duplex_timer);
}

static void
crisv32_eth_set_duplex(struct net_device *dev, enum duplex new_duplex)
{
        struct crisv32_ethernet_local *np = netdev_priv(dev);
        spin_lock(&np->transceiver_lock);
        if (np->current_duplex != new_duplex) {
                np->current_duplex = new_duplex;
                crisv32_eth_negotiate(dev);
        }
        spin_unlock(&np->transceiver_lock);
}

static int
crisv32_eth_probe_transceiver(struct net_device *dev)
{
        unsigned int phyid_high;
        unsigned int phyid_low;
        unsigned int oui;
        struct transceiver_ops *ops = NULL;
        struct crisv32_ethernet_local *np = netdev_priv(dev);

        /* Probe MDIO physical address. */
        for (np->mdio_phy_addr = 0;
             np->mdio_phy_addr <= 31; np->mdio_phy_addr++) {
                if (crisv32_eth_get_mdio_reg(dev, MII_BMSR) != 0xffff)
                        break;
        }

        if (np->mdio_phy_addr == 32)
                return -ENODEV;

        /* Get manufacturer. */
        phyid_high = crisv32_eth_get_mdio_reg(dev, MII_PHYSID1);
        phyid_low = crisv32_eth_get_mdio_reg(dev, MII_PHYSID2);
        
        oui = (phyid_high << 6) | (phyid_low >> 10);

        for (ops = &transceivers[0]; ops->oui; ops++) {
                if (ops->oui == oui)
                        break;
        }

        np->transceiver = ops;
        return 0;
}

static void
generic_check_speed(struct net_device *dev)
{
        unsigned long data;
        struct crisv32_ethernet_local *np = netdev_priv(dev);

        data = crisv32_eth_get_mdio_reg(dev, MII_ADVERTISE);
        if ((data & ADVERTISE_100FULL) ||
            (data & ADVERTISE_100HALF))
                np->current_speed = 100;
        else
                np->current_speed = 10; 
}

static void
generic_check_duplex(struct net_device *dev)
{
        unsigned long data;
        struct crisv32_ethernet_local *np = netdev_priv(dev);
        
        data = crisv32_eth_get_mdio_reg(dev, MII_ADVERTISE);
        if ((data & ADVERTISE_10FULL) ||
            (data & ADVERTISE_100FULL))
                np->full_duplex = 1;
        else
                np->full_duplex = 0;
}

static void
broadcom_check_speed(struct net_device *dev)
{
        unsigned long data;
        struct crisv32_ethernet_local *np = netdev_priv(dev);

        data = crisv32_eth_get_mdio_reg(dev, MDIO_AUX_CTRL_STATUS_REG);
        np->current_speed = (data & MDIO_BC_SPEED ? 100 : 10);
}

static void
broadcom_check_duplex(struct net_device *dev)
{
        unsigned long data;
        struct crisv32_ethernet_local *np = netdev_priv(dev);

        data = crisv32_eth_get_mdio_reg(dev, MDIO_AUX_CTRL_STATUS_REG);        
        np->full_duplex = (data & MDIO_BC_FULL_DUPLEX_IND) ? 1 : 0;
}

static void
tdk_check_speed(struct net_device *dev)
{
        unsigned long data;
        struct crisv32_ethernet_local *np = netdev_priv(dev);
        
        data = crisv32_eth_get_mdio_reg(dev, MDIO_TDK_DIAGNOSTIC_REG);
        np->current_speed = (data & MDIO_TDK_DIAGNOSTIC_RATE ? 100 : 10);
}

static void
tdk_check_duplex(struct net_device *dev)
{
        unsigned long data;
        struct crisv32_ethernet_local *np = netdev_priv(dev);

        data = crisv32_eth_get_mdio_reg(dev, MDIO_TDK_DIAGNOSTIC_REG);
        np->full_duplex = (data & MDIO_TDK_DIAGNOSTIC_DPLX) ? 1 : 0;

}

static void
intel_check_speed(struct net_device *dev)
{
        unsigned long data;
        struct crisv32_ethernet_local *np = netdev_priv(dev);
        data = crisv32_eth_get_mdio_reg(dev, MDIO_INT_STATUS_REG_2);
        np->current_speed = (data & MDIO_INT_SPEED ? 100 : 10);
}

static void
intel_check_duplex(struct net_device *dev)
{
        unsigned long data;
        struct crisv32_ethernet_local *np = netdev_priv(dev);
        
        data = crisv32_eth_get_mdio_reg(dev, MDIO_INT_STATUS_REG_2);        
        np->full_duplex = (data & MDIO_INT_FULL_DUPLEX_IND) ? 1 : 0;
}

static void
national_check_speed(struct net_device *dev)
{
        unsigned long data;
        struct crisv32_ethernet_local *np = netdev_priv(dev);

        data = crisv32_eth_get_mdio_reg(dev, MDIO_NAT_LINK_AN_REG);
        if (data & MDIO_NAT_1000)
                np->current_speed = 1000;
        else if (data & MDIO_NAT_100)
                np->current_speed = 100;
        else
                np->current_speed = 10; 
}

static void
national_check_duplex(struct net_device *dev)
{
        unsigned long data;
        struct crisv32_ethernet_local *np = netdev_priv(dev);
        
        data = crisv32_eth_get_mdio_reg(dev, MDIO_NAT_LINK_AN_REG);
        if (data & MDIO_NAT_FULL_DUPLEX_IND)
                np->full_duplex = 1;
        else
                np->full_duplex = 0;
}

static void
vitesse_check_speed(struct net_device *dev)
{
        unsigned long data;
        struct crisv32_ethernet_local *np = netdev_priv(dev);

        data = crisv32_eth_get_mdio_reg(dev, MDIO_VIT_AUX_STAT);
        if ((data & 0x18) == MDIO_VIT_1000)
                np->current_speed = 1000;
        else if ((data & 0x18) == MDIO_VIT_100)
                np->current_speed = 100;
        else
                np->current_speed = 10; 
}

static void
vitesse_check_duplex(struct net_device *dev)
{
        unsigned long data;
        struct crisv32_ethernet_local *np = netdev_priv(dev);

        data = crisv32_eth_get_mdio_reg(dev, MDIO_VIT_AUX_STAT);
        if (data & 0x20)
                np->full_duplex = 1;
        else
                np->full_duplex = 0;
}

static void
crisv32_eth_reset_tranceiver(struct net_device *dev)
{
        int i;
        unsigned short cmd;
        unsigned short data;
        struct crisv32_ethernet_local *np = netdev_priv(dev);

        data = crisv32_eth_get_mdio_reg(dev, MII_BMCR);

        cmd = (MDIO_START << 14)
                | (MDIO_WRITE << 12)
                | (np->mdio_phy_addr << 7)
                | (MII_BMCR << 2);

        crisv32_eth_send_mdio_cmd(dev, cmd, 1);

        data |= 0x8000;

        /* Magic value is number of bits. */
        for (i = 15; i >= 0; i--)
                crisv32_eth_send_mdio_bit(dev, GET_BIT(i, data));
}

static unsigned short
crisv32_eth_get_mdio_reg(struct net_device *dev, unsigned char reg_num)
{
        int i;
        unsigned short cmd;     /* Data to be sent on MDIO port. */
        unsigned short data;    /* Data read from MDIO. */
        struct crisv32_ethernet_local *np = netdev_priv(dev);

        /* Start of frame, OP Code, Physical Address, Register Address. */
        cmd = (MDIO_START << 14)
                | (MDIO_READ << 12)
                | (np->mdio_phy_addr << 7)
                | (reg_num << 2);

        crisv32_eth_send_mdio_cmd(dev, cmd, 0);

        data = 0;

        /* Receive data. Magic value is number of bits. */
        for (i = 15; i >= 0; i--)
                data |= (crisv32_eth_receive_mdio_bit(dev) << i);

        return data;
}

static void
crisv32_eth_set_mdio_reg(struct net_device *dev, unsigned char reg, int value)
{
        int bitCounter;
        unsigned short cmd;
        struct crisv32_ethernet_local *np = netdev_priv(dev);

        cmd = (MDIO_START << 14)
                | (MDIO_WRITE << 12)
                | (np->mdio_phy_addr << 7)
                | (reg << 2);
        
        crisv32_eth_send_mdio_cmd(dev, cmd, 1);

        /* Data... */
        for (bitCounter=15; bitCounter>=0 ; bitCounter--) {
                crisv32_eth_send_mdio_bit(dev, GET_BIT(bitCounter, value));
        }
}

static void
crisv32_eth_send_mdio_cmd(struct net_device *dev, unsigned short cmd,
                          int write_cmd)
{
        int i;
        unsigned char data = 0x2;

        /* Preamble. Magic value is number of bits. */
        for (i = 31; i >= 0; i--)
                crisv32_eth_send_mdio_bit(dev, GET_BIT(i, MDIO_PREAMBLE));

        for (i = 15; i >= 2; i--)
                crisv32_eth_send_mdio_bit(dev, GET_BIT(i, cmd));

        /* Turnaround. */
        for (i = 1; i >= 0; i--)
                if (write_cmd)
                        crisv32_eth_send_mdio_bit(dev, GET_BIT(i, data));
                else
                        crisv32_eth_receive_mdio_bit(dev);
}

static void
crisv32_eth_send_mdio_bit(struct net_device *dev, unsigned char bit)
{
        struct crisv32_ethernet_local *np = netdev_priv(dev);
        
        reg_eth_rw_mgm_ctrl mgm_ctrl = {
                .mdoe = regk_eth_yes,
                .mdio = bit & 1
        };

        REG_WR(eth, np->eth_inst, rw_mgm_ctrl, mgm_ctrl);

        udelay(1);

        mgm_ctrl.mdc = 1;
        REG_WR(eth, np->eth_inst, rw_mgm_ctrl, mgm_ctrl);

        udelay(1);
}

static unsigned char
crisv32_eth_receive_mdio_bit(struct net_device *dev)
{
        reg_eth_r_stat stat;
        reg_eth_rw_mgm_ctrl mgm_ctrl = {0};
        struct crisv32_ethernet_local *np = netdev_priv(dev);

        REG_WR(eth, np->eth_inst, rw_mgm_ctrl, mgm_ctrl);
        stat = REG_RD(eth, np->eth_inst, r_stat);

        udelay(1);

        mgm_ctrl.mdc = 1;
        REG_WR(eth, np->eth_inst, rw_mgm_ctrl, mgm_ctrl);

        udelay(1);
        return stat.mdio;
}

static void
crisv32_clear_network_leds(unsigned long priv)
{
        struct net_device *dev = (struct net_device*)priv;
        struct crisv32_ethernet_local *np = netdev_priv(dev);
        unsigned long flags;

        spin_lock_irqsave(&np->leds->led_lock, flags);
        if (np->leds->led_active && time_after(jiffies, 
                                               np->leds->led_next_time)) {
                crisv32_set_network_leds(LED_NOACTIVITY, dev);

                /* Set the earliest time we may set the LED */
                np->leds->led_next_time = jiffies + NET_FLASH_PAUSE;
                np->leds->led_active = 0;
        }
        spin_unlock_irqrestore(&np->leds->led_lock, flags);
}

static void
crisv32_set_network_leds(int active, struct net_device *dev)
{
        struct crisv32_ethernet_local *np = netdev_priv(dev);
        int light_leds = 0;

        if (np->leds->ledgrp == LED_GRP_NONE)
          return;

        if (active == LED_NOLINK) {
                if (dev == crisv32_dev[0])
                        np->leds->ifisup[0] = 0;
                else
                        np->leds->ifisup[1] = 0;
        }
        else if (active == LED_LINK) {
                if (dev == crisv32_dev[0])
                        np->leds->ifisup[0] = 1;
                else
                        np->leds->ifisup[1] = 1;
#if defined(CONFIG_ETRAX_NETWORK_LED_ON_WHEN_LINK) 
                light_leds = 1;
        } else {
                light_leds = (active == LED_NOACTIVITY);
#elif defined(CONFIG_ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY)
                light_leds = 0;
        } else {
                light_leds = (active == LED_ACTIVITY);
#else
#error "Define either CONFIG_ETRAX_NETWORK_LED_ON_WHEN_LINK or CONFIG_ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY"
#endif 
        }

        if (!use_network_leds) {
                // NET_LED_SET(np->leds->ledgrp,LED_OFF);
                return;
        }

        if (!np->current_speed) {
                /* Set link down if none of the interfaces that use this led
                   group is up */
                if ((np->leds->ifisup[0] + np->leds->ifisup[1]) == 0) {
#if defined(CONFIG_ETRAX_NETWORK_RED_ON_NO_CONNECTION)
                        /* Make LED red, link is down */
                        // NET_LED_SET(np->leds->ledgrp,LED_RED);
#else
                        // NET_LED_SET(np->leds->ledgrp,LED_OFF);
#endif  
                }
        }
        else if (light_leds) {
                if (np->current_speed == 10) {
                        // NET_LED_SET(np->leds->ledgrp,LED_ORANGE);
                } else {
                        // NET_LED_SET(np->leds->ledgrp,LED_GREEN);
                }
        }
        else {
                // NET_LED_SET(np->leds->ledgrp,LED_OFF);
        }
}

#ifdef CONFIG_NET_POLL_CONTROLLER
static void
crisv32_netpoll(struct net_device* netdev)
{
        crisv32rx_eth_interrupt(DMA0_INTR_VECT, netdev);
}
#endif

#ifdef CONFIG_CPU_FREQ
static int
crisv32_ethernet_freq_notifier(struct notifier_block *nb,
                               unsigned long val, void *data)
{
        struct cpufreq_freqs *freqs = data;
        if (val == CPUFREQ_POSTCHANGE) {
                int i;
                for (i = 0; i < 2; i++) {
                        struct net_device* dev = crisv32_dev[i];
                        unsigned short data;
                        if (dev == NULL)
                                continue;

                        data = crisv32_eth_get_mdio_reg(dev, MII_BMCR);
                        if (freqs->new == 200000)
                                data &= ~BMCR_PDOWN;
                        else
                                data |= BMCR_PDOWN;
                        crisv32_eth_set_mdio_reg(dev, MII_BMCR, data);
                }
        }
        return 0;
}
#endif

/*
 * Must be called with the np->lock held.
 */
static void crisv32_ethernet_bug(struct net_device *dev)
{
        struct crisv32_ethernet_local *np = netdev_priv(dev);
        dma_descr_data *dma_pos;
        dma_descr_data *in_dma_pos;
        reg_dma_rw_stat stat = {0};
        reg_dma_rw_stat in_stat = {0};
        int i;
                
        /* Get the current output dma position. */
        stat = REG_RD(dma, np->dma_out_inst, rw_stat);

#ifdef CONFIG_CRIS_MACH_ARTPEC3
        if (np->gigabit_mode) {
                dma_pos = crisv32_intmem_phys_to_virt(
                        REG_RD_INT(dma, np->dma_out_inst, rw_data));
                in_dma_pos = crisv32_intmem_phys_to_virt(
                        REG_RD_INT(dma, np->dma_in_inst, rw_data));
        } else
#endif
        {
                dma_pos = phys_to_virt(REG_RD_INT(dma, np->dma_out_inst, 
                                                  rw_data));
                in_dma_pos = phys_to_virt(REG_RD_INT(dma, np->dma_in_inst, 
                                                     rw_data));
        }
        in_stat = REG_RD(dma, np->dma_in_inst, rw_stat);
        
        printk("%s:\n"
               "stat.list_state=%x\n"
               "stat.mode=%x\n"
               "stat.stream_cmd_src=%x\n"
               "dma_pos=%x\n"
               "tx catch=%x active=%x\n"
               "packets=%d queue=%d\n"
               "intr_vect.r_vect=%x\n"
               "dma.r_masked_intr=%x dma.rw_ack_intr=%x "
               "dma.r_intr=%x dma.rw_intr_masked=%x\n"
               "eth.r_stat=%x\n",
               __func__,
               stat.list_state, stat.mode, stat.stream_cmd_src,
               (unsigned int)dma_pos,
               (unsigned int)&np->catch_tx_desc->descr,
               (unsigned int)&np->active_tx_desc->descr,
               np->txpackets,
               netif_queue_stopped(dev),
               REG_RD_INT(intr_vect, regi_irq, r_vect),
               REG_RD_INT(dma, np->dma_out_inst, r_masked_intr),
               REG_RD_INT(dma, np->dma_out_inst, rw_ack_intr),
               REG_RD_INT(dma, np->dma_out_inst, r_intr),
               REG_RD_INT(dma, np->dma_out_inst, rw_intr_mask),
               REG_RD_INT(eth, np->eth_inst, r_stat));

        printk("in_stat.list_state=%x\n"
               "in_stat.mode=%x\n"
               "in_stat.stream_cmd_src=%x\n"
               "in_dma_pos=%x\n"
               "rx last=%x prev=%x active=%x\n",
               in_stat.list_state, in_stat.mode, in_stat.stream_cmd_src,
               (unsigned int)in_dma_pos,
               (unsigned int)&np->last_rx_desc->descr,
               (unsigned int)&np->prev_rx_desc->descr,
               (unsigned int)&np->active_rx_desc->descr);
               

        printk("rx-descriptors:\n");
        for (i = 0; i < NBR_RX_DESC; i++) {
                printk("rxdesc[%d]=0x%x\n", i, (unsigned int)
                       virt_to_phys(&np->dma_rx_descr_list[i].descr));
                printk("rxdesc[%d].skb=0x%x\n", i,
                       (unsigned int)np->dma_rx_descr_list[i].skb);
                printk("rxdesc[%d].buf=0x%x\n", i,
                       (unsigned int)np->dma_rx_descr_list[i].descr.buf);
                printk("rxdesc[%d].after=0x%x\n", i,
                       (unsigned int)np->dma_rx_descr_list[i].descr.after);
                printk("rxdesc[%d].intr=%x\n", i,
                       np->dma_rx_descr_list[i].descr.intr);
                printk("rxdesc[%d].eol=%x\n", i,
                       np->dma_rx_descr_list[i].descr.eol);
                printk("rxdesc[%d].out_eop=%x\n", i,
                       np->dma_rx_descr_list[i].descr.out_eop);
                printk("rxdesc[%d].in_eop=%x\n", i,
                       np->dma_rx_descr_list[i].descr.in_eop);
                printk("rxdesc[%d].wait=%x\n", i,
                       np->dma_rx_descr_list[i].descr.wait);
        }
        printk("tx-descriptors:\n");
        for (i = 0; i < NBR_TX_DESC; i++) {
                printk("txdesc[%d]=0x%x\n", i, (unsigned int)
                       virt_to_phys(&np->dma_tx_descr_list[i].descr));
                printk("txdesc[%d].skb=0x%x\n", i,
                       (unsigned int)np->dma_tx_descr_list[i].skb);
                printk("txdesc[%d].buf=0x%x\n", i,
                       (unsigned int)np->dma_tx_descr_list[i].descr.buf);
                printk("txdesc[%d].after=0x%x\n", i,
                       (unsigned int)np->dma_tx_descr_list[i].descr.after);
                printk("txdesc[%d].intr=%x\n", i,
                       np->dma_tx_descr_list[i].descr.intr);
                printk("txdesc[%d].eol=%x\n", i,
                       np->dma_tx_descr_list[i].descr.eol);
                printk("txdesc[%d].out_eop=%x\n", i,
                       np->dma_tx_descr_list[i].descr.out_eop);
                printk("txdesc[%d].in_eop=%x\n", i,
                       np->dma_tx_descr_list[i].descr.in_eop);
                printk("txdesc[%d].wait=%x\n", i,
                       np->dma_tx_descr_list[i].descr.wait);
        }
}


static int
crisv32_init_module(void)
{
        return crisv32_ethernet_init();
}

static int __init
crisv32_boot_setup(char* str)
{
        struct sockaddr sa = {0};
        int i;

        /* Parse the colon separated Ethernet station address */
        for (i = 0; i <  ETH_ALEN; i++) {
                unsigned int tmp;
                if (sscanf(str + 3*i, "%2x", &tmp) != 1) {
                        printk(KERN_WARNING "Malformed station address");
                        return 0;
                }
                sa.sa_data[i] = (char)tmp;
        }

        default_mac_iface0 = sa;
        return 1;
}

__setup("crisv32_eth=", crisv32_boot_setup);

module_init(crisv32_init_module);

---