00001 //x353.h 00002 // fpga definitions (should match those of Verilog sources) 00003 #ifdef CONFIG_ETRAX_313 00004 #define X313_MINMODREV 0x03130050 // minimal fpga model/rev that should work with current driver 00005 #define X313_MAXMODREV 0x0313005f // maximal fpga model/rev that should work with current driver 00006 #endif 00007 #ifdef CONFIG_ETRAX_323 00008 #define X313_MINMODREV 0x03230000 // minimal fpga model/rev that should work with current driver 00009 #define X313_MAXMODREV 0x0323003f // maximal fpga model/rev that should work with current driver 00010 #endif 00011 00012 #ifdef CONFIG_ETRAX_333 00013 #define X313_MINMODREV 0x03331000 // minimal fpga model/rev that should work with current driver 00014 #define X313_MAXMODREV 0x0333103f // maximal fpga model/rev that should work with current driver 00015 #endif 00016 00017 #ifdef CONFIG_ETRAX_ELPHEL353 00018 #define X313_MINMODREV 0x03531015 // minimal fpga model/rev that should work with current driver 00019 #define X313_MAXMODREV 0x035330ff // maximal fpga model/rev that should work with current driver 00020 #endif 00021 00022 #define X313__RA__STATUS 0x10 // read status register 00023 #define X313__RA__IRQS 0x11 // read interrupt register 00024 #define X313__RA__TRIGPH 0x12 // read trigger phase (line/pixel of readout when trigger came) 00025 #define X313__RA__MODEL 0x13 // read model number/revision of FPGA 00026 #define X313__RA__TABLE 0x14 // readback FPGA tables (not all of them, may be removed later) 00027 #ifdef CONFIG_ETRAX_ELPHEL353 00028 #define X313__RA__XFERCNTR 0x14 // readback compressor transfer counter (24 bits, counts 32-byutes chunks) 00029 #define X313__RA__HIGHFREQ 0x15 // 32-bit accumulated value oif hi-frequency components (filter is table defined) - (since 03533014) 00030 00031 00032 #define X313__RA__USB 0x60 // read USB data 00033 #define X313__RA__IOPINS 0x70 // read state of 12 I/O pins 00034 // bit 0 - SCL1 00035 // bit 1 - SDA1 00036 // bit 2 - XRST 00037 // bit 3 - AUXCLK 00038 // bit 4 - EXPS 00039 // bit 5 - TRIG 00040 #define X313__RA__SENSFPGA 0x74 // - currently will read the same s0x70. Bit 16 (0x10000) is multiplexed state of 1 of 3 pins 00041 #define SFPGA_RD_BIT 16 // Obsolete???? 00042 #define I2C_FRAME_NUMBER 0x16 // Read 3 LSB of frame number as seen by I2C controller and i2c busy (0x10000) 00043 #endif 00044 00045 #ifdef CONFIG_ETRAX_333 00046 #define X313__RA__USB 0x60 // read USB data 00047 #define X313__RA__IOPINS 0x70 // read state of 6 I/O pins (12 in 353) 00048 // bit 0 - SCL1 00049 // bit 1 - SDA1 00050 // bit 2 - XRST 00051 // bit 3 - AUXCLK 00052 // bit 4 - EXPS 00053 // bit 5 - TRIG 00054 #endif 00055 00056 00057 #define X313__RA__SDCH0 0x20 00058 #define X313__RA__SDCH1 0x24 00059 #define X313__RA__SDCH2 0x28 00060 #define X313__RA__SDCH3 0x2c 00061 #define X313__RA__SDBUF3 0x30 // 30.37 - data window for PIO access (channel3) 00062 00063 #ifdef CONFIG_ETRAX_333 00064 #define X313_SR__DCM_RDY 23 00065 #define X313_SR__DCM_EARLY 22 00066 #define X313_SR__DCM_LATE 21 00067 #endif 00068 00069 #ifdef CONFIG_ETRAX_ELPHEL353 00070 00071 #define X313_SR__CLK_LOCKED 28 00072 #define X313_SR__SENS_DCM_OVFL 27 00073 #define X313_SR__SENS_DCM_LOCKED 26 00074 #define X313_SR__SENS_DCM_RDY 25 00075 00076 #define X313_SR__SENS_DCM_EARLY 24 00077 #define X313_SR__SENS_DCM_LATE 23 00078 // new meaning: 00079 #define X313_SR__SENS_DCM_ERROR 24 // if 0, the data strobe is in a middle of >= T/2 stable data (never the case with 96MHz at slow drivers) 00080 // if 1 - at least one of the before/after strobes return different data than the actual strobe 00081 #define X313_SR__SENS_DCM_LATE 23 // "1" - needs phase increase ( 80 for 90 degrees, 20 - for fine) 00082 00083 #define X313_SENSOR_PHASE ((port_csp0_addr[X313__RA__STATUS] >> X313_SR__SENS_DCM_LATE ) & 3) 00084 00085 00086 #define X313_SR__DCM_OVFL 22 00087 #define X313_SR__DCM_LOCKED 21 00088 #define X313_SR__DCM_RDY 20 00089 #define X313_SR__DCM_EARLY 19 00090 #define X313_SR__DCM_LATE 18 00091 00092 // #define X313_SR__TRIG 20 // TRIG input state 00093 #define X313_SR__DMA_EMPTY 17 // Dma buffer empty (wait after compressor is done) 00094 #define X313_SR__DONE_CMPRS 16 // Compressor done (IRQ available) 00095 #define X313_SR__DONE_CI 15 // Compressor finished reading SDRAM (IRQ available) 00096 #define X313_SR__DCCRDY 14 // Next 128 (or just the last in frame) DC components are ready 00097 // to be read out. 00098 #define X313_SR__DONE 13 // reset reset by writing to X313_WA_TRIG 00099 // 00 - off 00100 // 01 - waiting fo frame sync to start acquisition 00101 // 10 - waiting for trigger 00102 // 11 - acquisition in progr 00103 #define X313_SR__SENST1 12 00104 #define X313_SR__SENST0 11 00105 #define X313_SR__NXTFR3 10 00106 #define X313_SR__NXTFR2 9 00107 #define X313_SR__NXTFR1 8 00108 #define X313_SR__NXTFR0 7 00109 #define X313_SR__PIOWEMPTY 6 00110 #define X313_SR__PIORDY 5 00111 #define X313_SR__CH2RDY 4 00112 #define X313_SR__CH1RDY 3 00113 #define X313_SR__CH0RDY 2 00114 // #define X313_SR__SCL1 3 00115 // #define X313_SR__SDA1 2 00116 #define X313_SR__SCL0 1 00117 #define X313_SR__SDA0 0 00118 // Will chnage 00119 #define X313_PIOR__SCL1 0 00120 #define X313_PIOR__SDA1 1 00121 #define X313_PIOR__XRST 2 00122 #define X313_PIOR__AUXCLK 3 00123 #define X313_PIOR__EXPS 4 00124 #define X313_PIOR__TRIG 5 00125 00126 00127 00128 #else 00129 #define X313_SR__TRIG 20 // TRIG input state 00130 #define X313_SR__DMA_EMPTY 19 // Dma buffer empty (wait after compressor is done) 00131 #define X313_SR__DONE_CMPRS 18 // Compressor done (IRQ available) 00132 #define X313_SR__DONE_CI 17 // Compressor finished reading SDRAM (IRQ available) 00133 #define X313_SR__DCCRDY 16 // Next 128 (or just the last in frame) DC components are ready 00134 // to be read out. 00135 #define X313_SR__DONE 15 // reset reset by writing to X313_WA_TRIG 00136 // 00 - off 00137 // 01 - waiting fo frame sync to start acquisition 00138 // 10 - waiting for trigger 00139 // 11 - acquisition in progr 00140 #define X313_SR__SENST1 14 00141 #define X313_SR__SENST0 13 00142 #define X313_SR__NXTFR3 12 00143 #define X313_SR__NXTFR2 11 00144 #define X313_SR__NXTFR1 10 00145 #define X313_SR__NXTFR0 9 00146 #define X313_SR__PIOWEMPTY 8 00147 #define X313_SR__PIORDY 7 00148 #define X313_SR__CH2RDY 6 00149 #define X313_SR__CH1RDY 5 00150 #define X313_SR__CH0RDY 4 00151 #define X313_SR__SCL1 3 00152 #define X313_SR__SDA1 2 00153 #define X313_SR__SCL0 1 00154 #define X313_SR__SDA0 0 00155 #endif 00156 // valid for model 323 00157 #define X313_SR__X323_SI 0 00158 00159 00160 00161 #define X313_SR(x) ((port_csp0_addr[X313__RA__STATUS] >> X313_SR__##x ) & 1) 00162 #define X313_PIOR(x) ((port_csp0_addr[X313__RA__IOPINS] >> X313_PIOR__##x ) & 1) 00163 00164 00165 #define X313_IR__VACT 0 // start of VACT pulse 00166 #define X313_IR__XINT 1 // external enterrupt 00167 #define X313_IR__XFEROVR 2 // DMA xfer over 00168 #define X313_IR__DONE 3 // DMA xfer over, persistent till reset through... 00169 #define X313_IR__EOT 4 00170 #define X313_IR__DCC 5 // Next 128 16-bit DC components (and HF too) are ready (or the partial block - last in frame). 00171 // Reset when all 128 are read out or DCC mode is reset (0 is written to bit 12 register X313_WA_SDCH3_CTL0 - 0x2c) 00172 #define X313_IR__DONE_INPUT 6 // persistent till compressor reset/restarted 00173 #define X313_IR__DONE_COMPRESS 7 // persistent till compressor reset/restarted 00174 #define X313_IR__SMART 8 // Single cycle, does not need restart, configurable to wait for VACT, always at VACT if no compression is underway 00175 00176 00177 #ifdef CONFIG_ETRAX_ELPHEL353 00178 #define X313_IR(x) ((port_csp0_addr[X313__RA__IRQS] >> ( X313_IR__##x ) + 8) & 1) 00179 #else 00180 #ifdef CONFIG_ETRAX_333 00181 #define X313_IR(x) ((port_csp0_addr[X313__RA__IRQS] >> ( X313_IR__##x ) + 8) & 1) 00182 #else 00183 #define X313_IR(x) ((port_csp0_addr[X313__RA__IRQS] >> X313_IR__##x ) & 1) 00184 #endif 00185 #endif 00186 /* peripherial write addresses (relative to csp0, in long words) */ 00187 #define X313_WA_WCTL 0 // write control register - 32 00188 #define X313_WA_DMACR 1 // DMA control register: 00189 // 17: DMA enable 00190 // 16: 0- raw, 1 - JPEG 00191 // 15-10: not used 00192 // 0-9: line length in long words 00193 #define X313_WA_SENSFPN 2 // Sensor/FPN control register: 00194 // [10] - testmode - if 1 generates gradient data (as Zoran chips) where pixel value = horizontal position 00195 // [9:7] - submode - subtract background (8 bits) mode (use di[7:0]): 00196 // 000 - no subtraction; 00197 // 001 - (finest) subtract 8 bit bkgnd from 12 bits pixels 00198 // 010 - shift 8bit bkgnd 1 bit left before applying 00199 // 011 - shift 8bit bkgnd 2 bits left before applying 00200 // 100 - shift 8bit bkgnd 2 bits left before applying 00201 // 101 - shift 8bit bkgnd 2 bits left before applying 00202 // fpn data to subtract should be a little less to add a "fat zero" 00203 // [6:4] - mpymode sensitivity correction mode (use di[15:8]): 00204 // 000 - no correction 00205 // 001 - fine correction (+/-3.125%) 00206 // 010 - fine correction (+/-6.25%) 00207 // 011 - fine correction (+/-12.5%) 00208 // 100 - +/- 25% 00209 // 101 - +/- 50% 00210 // [3] - wdth - word width: 0 - 8 bit, 1 - 16 bit (5 MSB == 0) 00211 // [2:0] scaling of 11 bit FPN result to fit in 8bit output: 00212 // 00 - default - use [9:1] 00213 // 01 - use [10:2] - to protect from saturation after applying mpymode 00214 // nominal range - 0..127 00215 // 10 - use [7:0] before saturation, "digital gain" == 4 (maximal) 00216 // 11 - use [8:1] before saturation, "digital gain" == 2 00217 00218 // 31-8: not used 00219 // 7: 0 - normal, 1 - test mode (as Zoran) 00220 // 6-5: subtract FPN mode: 00221 // 0 - no subtraction 00222 // 1 (fine) - subtract 8-bit FPN from 10-bit pixel 00223 // 2 - multiply FPN by 2 before subtracting 00224 // 3 - multiply FPN by 4 before subtracting (full scfpcfale) 00225 // negative result is replaced by 0, decrease FPN data before applying for "fat 0" 00226 // 4-3: muliply by inverse sensitivity (sensitivity correction) mode: 00227 // 0 - no correction 00228 // 1 - fine (+/- 12.5%) 00229 // 2 - medium (+/- 25%) 00230 // 3 - maximal (+/- 50%) 00231 // 2: pixel depth: 00232 // 0 - 8 bits/pixel (needed for JPEG encoding) 00233 // 1 - 16 bits/pixel (only 11 LSBs are non-zero) 00234 // 1-0: scale (8 bit mode only): 00235 // 0 - full scale corresponds to sensor full scale if no correction was applied 00236 // 1 - divide by 2. This will guarantee against saturation after sensitivity correction was 00237 // applied. Nominal output range - 0..127 00238 // 2 - multiply by 4 (use 8 lower bits from sensor data) 00239 // 3 - multiply by 2 00240 // Result data is saturated by 255 00241 #define X313_WA_VIRTTRIG 3 // Virtual trigger threshold 00242 // 31-22 not used 00243 // 21-0 Trigger will fire if sum of pixels in a line 00244 // (after FPN processig) is more than this value. 00245 // Disabled if 0 - selected real (electrical) external trigger 00246 #define X313_WA_TRIG 4 // Sensor triggrring 00247 // 31-3: not used 00248 // 2: Enable sensor (0 - abort at once) 00249 // 1: External Trigger (0 - internal) 00250 // 0: continuous acquisition (0 - single "frame" - actually number of lines specified) 00251 #define X313_WA_NLINES 5 // number of lines to acquire (afer trigger) 00252 // 31-11: not used 00253 // 10-0 : number of lines to acquire (in a frame or after the external trigger) 00254 //#define X313_WA_IRQM 6 // Interrupt mask (1 - enable, 0 - reset all but done) 00255 // 31-04: not used 00256 // 3: Done. Reset by writing to X313_WA_TRIG 00257 // 2: frame acquisition over 00258 // 1: external trigger 00259 // 0: frame sync (vacts) 00260 #define X313_WA_DCDC 7 // sensor DC-DC converter frequency settings 00261 // 31-05: not used 00262 // 4-0 0 - use internal clock (not sync) 00263 // 1..31 use divided pixel clock 00264 // for 20MHz use 5'h10, 00265 // else - N= (Fpix[MHz]/1.2)-1, if Fpix=20MHz, 00266 // N= 15.7->16=5'h10 00267 00268 #ifdef CONFIG_ETRAX_ELPHEL353 00269 #define X313_WA_DCM 8 // SDRAM clock phase shift 00270 // #define X3X3_RSTSENSDCM {port_csp0_addr[X313_WA_DCM]=0x30;} // needed after changing frequency to restart sensor DCM 00271 #define X3X3_RSTSENSDCM {port_csp0_addr[X313_WA_DCM]=0xf0;} // reset 90 degrees here too 00272 #define X3X3_SENSDCM_INC90 {port_csp0_addr[X313_WA_DCM]=0x80;} // switch clock phase in precise 90-degree increments 00273 #define X3X3_SENSDCM_DEC90 {port_csp0_addr[X313_WA_DCM]=0x40;} // switch clock phase in precise 90-degree increments 00274 // NOTE fine steps range is limited, combine with 90-degree steps when needed 00275 #define X3X3_SENSDCM_INC {port_csp0_addr[X313_WA_DCM]=0x20;} // switch clock phase in fine steps (~110 for 90 degrees @96MHz) 00276 #define X3X3_SENSDCM_DEC {port_csp0_addr[X313_WA_DCM]=0x10;} // switch clock phase in fine steps (~110 for 90 degrees @96MHz) 00277 #define X3X3_SENSDCM_NOP {port_csp0_addr[X313_WA_DCM]=0x0;} // resets DCM errors (before measuring sensor phase) 00278 00279 #else 00280 #ifdef CONFIG_ETRAX_333 00281 #define X313_WA_DCM 8 // SDRAM clock phase shift 00282 // 0 - nop 00283 // 1 - increase 00284 // 2 - decrease 00285 // 3 - reset to default 00286 #define X3X3_RSTSENSDCM {port_csp0_addr[X313_WA_DCM]=0x30;} // will do nothing for 333 00287 #endif 00288 #endif 00289 #define X313_WA_COLOR_SAT 9 // bits 9: 0 - Cb (blue) color saturation. 0x90 (default) for saturation =1.0 00290 // bits 25:16 - Cr (red) color saturation. 0xb6 (default) for saturation =1.0 00291 #define DEFAULT_COLOR_SATURATION_BLUE 0x90 // 100*realtive saturation blue 00292 #define DEFAULT_COLOR_SATURATION_RED 0xb6 // 100*realtive saturation red 00293 00294 #define X313_WA_FRAMESYNC_DLY 0x0a // Delay frame sync interrupt by number of lines (default - 0) 00295 00296 00297 #define X313_WA_COMP_CMD 0x0c 00298 #ifdef CONFIG_ETRAX_ELPHEL353 00299 #define X313_WA_COMP_TA 0x0e 00300 #define X313_WA_COMP_TD 0x0f 00301 #define X313_WA_MCUNUM 0x0d 00302 #define X313_WA_SMART_IRQ 0x1a // configure smart IRQ (3-en/2-dis "smart" mode - waiting for next frame sync for early compression done) 00303 // 0xc - en/0x8 - dis waiting for DMA FIFO empty 00304 #define X313_WA_DCM_RST 0x1b // async reset of the system DCM 00305 #define X313_WA_IRQ_RST 0x1c // reset selected interrupt bits 00306 #define X313_WA_IRQ_DIS 0x1d // disable selected interrupt bits (mask) 00307 #define X313_WA_IRQ_ENA 0x1e // enable selected interrupt bits 00308 #define X313_WA_IRQ_WVECT 0x1f // write vector number (in bits [0:7], [11:8] - interrupt number (0..15) 00309 #define X313_WA_HIST_POS 0x40 00310 #define X313_WA_HIST_SIZE 0x41 00311 #define X313_WA_HIST_ADDR 0x42 00312 #define X313_RA_HIST_DATA 0x43 // use CSP4 with wait cycles to have a pulse 00313 #define X313_WA_RTC_USEC 0x44 00314 #define X313_WA_RTC_SEC 0x45 // sets both seconds and microseconds, so should be written second 00315 #define X313_WA_RTC_CORR 0x46 00316 #define X313_WA_RTC_LATCH 0x47 00317 #define X313_RA_RTC_USEC 0x44 00318 #define X313_RA_RTC_SEC 0x45 00319 #define X313_WA_TIMESTAMP 0x48 // 0 - no, 1 - normal frames, 2 - photofinish 00320 00321 // following registers accept 32-bit data words to be sent as 4 (or less) i2c command, that consists of 00322 // start, slave address (MSB), register address (bits 16..23), and 2 bytes of data (MSB first). 00323 // For single-byte registers LSB of the data word is not used, data byte uses bits 8..15 00324 // Example 0x902b0010 - write 0x0010 to register 0x2b of slave 0x90 00325 // Writes use relative (to the current frame) and absolute (modulo 8) addresses (readable through I2C_FRAME_NUMBER) 00326 // When using absolute addressing writing to the frame one before current will effectively write to the current frame, 00327 // so if new frame happens during writing - data will not be lost - it will transferred to the next frame. 00328 // Each frame buffer can hold 63 commands, current frame can process unlimited number of commands as long as FIFO does not have 00329 // more than 63 at any given moment. 00330 00331 00332 #define X313_I2C_FRAME0 0x50 // write command to be sent at frame number 0 (modulo 8) - see I2C_FRAME_NUMBER, 3 LSBs 00333 #define X313_I2C_FRAME1 0x51 // same for frame number 1 00334 #define X313_I2C_FRAME2 0x52 // same for frame number 1 00335 #define X313_I2C_FRAME3 0x53 // same for frame number 1 00336 #define X313_I2C_FRAME4 0x54 // same for frame number 1 00337 #define X313_I2C_FRAME5 0x55 // same for frame number 1 00338 #define X313_I2C_FRAME6 0x56 // same for frame number 1 00339 #define X313_I2C_FRAME7 0x57 // same for frame number 1 00340 #define X313_I2C_ASAP 0x58 // write command to be sent to sensor ASAP 00341 #define X313_I2C_NEXT 0x59 // write command to be sent after next frame start 00342 #define X313_I2C_NEXT2 0x5a // write command to be sent after next 2 frame starts 00343 #define X313_I2C_NEXT3 0x5b // write command to be sent after next 2 frame starts 00344 #define X313_I2C_NEXT4 0x5c // write command to be sent after next 2 frame starts 00345 #define X313_I2C_NEXT5 0x5d // write command to be sent after next 2 frame starts 00346 #define X313_I2C_NEXT6 0x5e // write command to be sent after next 2 frame starts 00347 #define X313_I2C_CMD 0x5f // write command to i2c controller, command consists of several independent bit fields 00348 // below data that can be written to port_csp0_addr[X313_I2C_CMD], OR-ed 00349 #define X3X3_SET_I2C_DLY(x) (0x100 | ((x) & 0xff)) 00350 #define X3X3_SET_I2C_BYTES(x) (0x800 | (((x)<<9) & 0x600)) 00351 #define X3X3_I2C_RUN_BITS 0x3000 // can not be combined with X3X3_I2C_RESET 00352 #define X3X3_I2C_STOP_BITS 0x2000 00353 #define X3X3_I2C_RESET_BITS 0x4000 00354 00355 #define X3X3_I2C_IS_BUSY (((port_csp0_addr[I2C_FRAME_NUMBER] | \ 00356 port_csp0_addr[I2C_FRAME_NUMBER] | \ 00357 port_csp0_addr[I2C_FRAME_NUMBER] | \ 00358 port_csp0_addr[I2C_FRAME_NUMBER] | \ 00359 port_csp0_addr[I2C_FRAME_NUMBER] ) & 0x10000)?1:0) 00360 #define X3X3_I2C_FRAME (port_csp0_addr[I2C_FRAME_NUMBER] & 0x7) 00361 #define X3X3_I2C_SEND2(a,s,r,d) {port_csp0_addr[a] = (s<<24) | ((r & 0xff) << 16) | (d & 0xffff) ; X3X3_AFTERWRITE ;} 00362 #define X3X3_I2C_SEND1(a,s,r,d) {port_csp0_addr[a] = (s<<24) | ((r & 0xff) << 16) | ((d & 0xff) << 8) ; X3X3_AFTERWRITE ;} 00363 00364 #define X3X3_GAMMA_PAGE ((port_csp0_addr[I2C_FRAME_NUMBER] & 0x20000)?1:0) // gamma table page (0/1) currently used 00365 00366 #define X3X3_I2C_STOP_WAIT {port_csp0_addr[X313_I2C_CMD]=X3X3_I2C_STOP_BITS; while (X3X3_I2C_IS_BUSY) ; } 00367 #define X3X3_I2C_RUN {port_csp0_addr[X313_I2C_CMD]=X3X3_I2C_RUN_BITS ; X3X3_AFTERWRITE ;} 00368 #define X3X3_I2C_RESET_WAIT {port_csp0_addr[X313_I2C_CMD]=X3X3_I2C_RESET_BITS; while (X3X3_I2C_IS_BUSY) ; } 00369 00370 // [14] - reset all FIFO (takes 16 clock pulses), stop i2c until run command (can not be combined with "run") 00371 // [13] - if 1 - use [12] to run/stop i2c controller (needed to be stopped and confirmed not busy before software i2c) 00372 // [12] - run/stop i2c (when [13] == 1 00373 // [11] - if 1, use [10:9] to set command bytes to send after slave address (0..3) 00374 // [10:9] - number of bytes to send, valid if [11] is set. For Micron sensors - use 3 00375 // [8] - set duration of quarter i2c cycle in system clock cycles - nominal value 100 (0x64) fro 160MHz 00376 // [7:0] - duration of quarter i2c cycle (applied if [8] is set) 00377 00378 00379 #define X313_WA_USB 0x60 // ... 0x6f 00380 #define X313_WA_IOPINS 0x70 // bits [27:26] select the source of the control word: 00381 // to eliminate the need for a shadow registers made that a 00382 // dibit=0 - no change 00383 // dibit=1 - set en=1, d=0 00384 // dibit=2 - set en=1, d=1 00385 // dibit=3 - set en=0, d=0 00386 // 0 - use bits [25:0] of the control word (0 - data0, 1 - enable out0, 2 - data1, ..., 11 - enable out5) 00387 // 1 - use channel A (USB)? 00388 // 2 - use channel B (tbd) 00389 // 3 - use channel C (tbd) 00390 #define X313_WA_SENSFPGA 0x74 //Control programming of external FPGA on the sensor/sensor multiplexor board 00391 #define X313_WA_CAMSYNCTRIG 0x78 // trigger condition, 0 - internal, else dibits ((use<<1) | level) for each GPIO[11:0] pin 00392 #define X313_WA_CAMSYNCDLY 0x79 // trigger delay, 32 bits in pixel clocks 00393 #define X313_WA_CAMSYNCOUT 0x7a // trigger output to GPIO, dibits ((use << 1) | level_when_active). Bit 24 - test mode, when GPIO[11:10] are controlled by other internal signals 00394 #define X313_WA_CAMSYNCPER 0x7b // output sync period (32 bits, in pixel clocks). 0- stop. 1..256 - single, >=256 repetitive with specified period. 00395 00396 00397 00398 /* 00399 #define SFPGA_TDI_HIGH 0x03 00400 #define SFPGA_TDI_LOW 0x02 00401 #define SFPGA_TMS_HIGH 0x0c 00402 #define SFPGA_TMS_LOW 0x08 00403 #define SFPGA_TCK_HIGH 0x30 00404 #define SFPGA_TCK_LOW 0x20 00405 #define SFPGA_PROG_HIGH 0xc0 00406 #define SFPGA_PROG_LOW 0x80 00407 #define SFPGA_PGMEN_HIGH 0x300 00408 #define SFPGA_PGMEN_LOW 0x200 00409 #define SFPGA_RD_SENSPGMPIN 0x80000 00410 #define SFPGA_RD_TDO 0x90000 00411 #define SFPGA_RD_DONE 0xa0000 00412 */ 00413 #define SFPGA_TDI_BIT 0x0 00414 #define SFPGA_TMS_BIT 0x2 00415 #define SFPGA_TCK_BIT 0x4 00416 #define SFPGA_PROG_BIT 0x6 00417 #define SFPGA_PGMEN_BIT 0x8 00418 #define SFPGA_RD_SENSPGMPIN 0x80000 00419 #define SFPGA_RD_TDO 0x90000 00420 #define SFPGA_RD_DONE 0xa0000 00421 00422 00423 00424 //19:16 - 0xb..0xf - no changes 00425 // Mulptiplex status signals into a single line 00426 // - 0xa - select xfpgadone 00427 // - 0x9 - select xfpgatdo 00428 // - 0x8 - select senspgmin (default) 00429 // - 0x0..0x7 - no changes 00430 //15:10 - not used 00431 // 9: 8 - 3 - set xpgmen, 00432 // - 2 - reset xpgmen, 00433 // - 0, 1 - no changes to xpgmen 00434 // 7: 6 - 3 - set xfpgaprog, 00435 // - 2 - reset xfpgaprog, 00436 // - 0, 1 - no changes to xfpgaprog 00437 // 5: 4 - 3 - set xfpgatck, 00438 // - 2 - reset xfpgatck, 00439 // - 0, 1 - no changes to xfpgatck 00440 // 3: 2 - 3 - set xfpgatms, 00441 // - 2 - reset xfpgatms, 00442 // - 0, 1 - no changes to xfpgatms 00443 // 1: 0 - 3 - set xfpgatdi, 00444 // - 2 - reset xfpgatdi, 00445 // - 0, 1 - no changes to xfpgatdi 00446 00447 00448 00449 00450 #else 00451 #ifdef CONFIG_ETRAX_333 00452 #define X313_WA_COMP_TA 0x0e 00453 #define X313_WA_COMP_TD 0x0f 00454 #define X313_WA_MCUNUM 0x0d 00455 #define X313_WA_IRQ_RST 0x1c // reset selected interrupt bits 00456 #define X313_WA_IRQ_DIS 0x1d // disable selected interrupt bits (mask) 00457 #define X313_WA_IRQ_ENA 0x1e // enable selected interrupt bits 00458 #define X313_WA_IRQ_WVECT 0x1f // write vector number (in bits [0:7], [11:8] - interrupt number (0..15) 00459 #define X313_WA_HIST_POS 0x40 00460 #define X313_WA_HIST_SIZE 0x41 00461 #define X313_WA_HIST_ADDR 0x42 00462 #define X313_RA_HIST_DATA 0x43 // use CSP4 with wait cycles to have a pulse 00463 #define X313_WA_RTC_USEC 0x44 00464 #define X313_WA_RTC_SEC 0x45 00465 #define X313_WA_RTC_CORR 0x46 00466 #define X313_WA_RTC_LATCH 0x47 00467 #define X313_RA_RTC_USEC 0x44 00468 #define X313_RA_RTC_SEC 0x45 00469 #define X313_WA_TIMESTAMP 0x48 // 0 - no, 1 - normal frames, 2 - photofinish 00470 #define X313_WA_USB 0x60 // ... 0x6f 00471 #define X313_WA_IOPINS 0x70 // bits [13:12] selecte of the source of the control word: 00472 // 0 - use bits [11:0] of the control word (0 - data0, 1 - enable out0, 2 - data1, ..., 11 - enable out5) 00473 // 1 - use channel A (USB)? 00474 // 2 - use channel B (tbd) 00475 // 3 - use channel C (tbd) 00476 #else 00477 00478 00479 00480 #define X313_WA_IRQM 6 // Interrupt mask (1 - enable, 0 - reset all but done) 00481 // 31-04: not used 00482 // 3: Done. Reset by writing to X313_WA_TRIG 00483 // 2: frame acquisition over 00484 // 1: external trigger 00485 // 0: frame sync (vacts) 00486 #define X313_WA_COMP_TA 0x0d 00487 #define X313_WA_COMP_TD 0x0e 00488 #define X313_WA_MCUNUM 0x0f 00489 #endif 00490 #endif 00491 00492 // NOTE: Important note (issue came out with faster ETRAX FS). Due to write pipe and shared r/w addresses 00493 // it is not possible to read from registers 0x20.0x2f TWO cycles after any write to FPGA 00494 // The following dummy read will take 2 bus cycles 00495 #define X3X3_AFTERWRITE {if (!port_csp0_addr[X313__RA__MODEL]) printk ("model=0");} //just to be sure this read will not be optimized out 00496 #define x3x3_DELAY(x) {int iiii; for (iiii=0; iiii < (x); iiii++) X3X3_AFTERWRITE ; } 00497 00498 #define X313_WA_SDCH0_CTL0 0x20 // SDRAM control for Channel 0 - writing causes initialization of the channel 00499 //---353--- 00500 // 20 | | Channel 0 (16 bit data sensor->SDRAM) | Initialize channel: | (mode 0) | 00501 // | 31-16 | not used | 1) set address to startAddres | 31-30 | nbuf[1:0] | 00502 // | 15 | mode: 0 - 256x1 16-bit (or 512x1 bytes) | (word at address 01 with other | 29-18 | ntileY[11:0] | 00503 // | | 1 - 18x9 16 bit (or 18x18 bytes) | startAddress bits should be | 17-16 | ntileX[8:7] | 00504 // | | mode should be set to 0 for channel 0 | written earlier; | | | 00505 // | 14 | WnR - Write/not read. Should be 1 for channel 0 | 2) set nbuf[1:0] to 0 | 15-00 | Same as written | 00506 // | 13 | depend. Should be set to 1 if needed to synchronize | | | | 00507 // | | reading from SDRAM to writing from sensor | | | | 00508 // | 12-00 | frame start address startAddr[20:8]. Addressed are | | | | 00509 // | | 16-bit words, low 8 bits are 0 (aligned to 256 word | | | | 00510 // | | page boundary | | | | 00511 //---333--- 00512 // 20 | | Channel 0 (16 bit data sensor->SDRAM) | Initialize channel: | (mode 0) | 00513 // | 31-16 | not used | 1) set address to startAddres | 31-30 | nbuf[1:0] | 00514 // | 15 | mode: 0 - 256x1 16-bit (or 512x1 bytes) | (word at address 01 with other | 29-18 | ntileY[11:0] | 00515 // | | 1 - 18x9 16 bit (or 18x18 bytes) | startAddress bits should be | 17-16 | ntileX[8:7] | 00516 // | | mode should be set to 0 for channel 0 | written earlier; | | | 00517 // | 14 | WnR - Write/not read. Should be 1 for channel 0 | 2) set nbuf[1:0] to 0 | 15-00 | Same as written | 00518 // | 13 | depend. Should be set to 1 if needed to synchronize | | | | 00519 // | | reading from SDRAM to writing from sensor | | | | 00520 // | 12 | not used | | | | 00521 // | 11-00 | frame start address startAddr[19:8]. Addressed are | | | | 00522 // | | 16-bit words, low 8 bits are 0 (aligned to 256 word | | | | 00523 // | | page boundary | | | | 00524 //---313/323--- 00525 // 31-16 | not used | 1) set address to startAddres | 31 | nbuf (buffer page number) 00526 // 15 | mode: 0 - 128x1 16-bit (or 256x1 bytes) | (word at address 01 with other | | for ping-pong operation 00527 // | 1 - 16x8 16 bit (or 16x16 bytes) | startAddress bits should be | 30-19 | tileY (12 bits) if mode=0 00528 // | mode should be set to 0 for channel 0 | written earlier; | 18-16 | tileX ( 2 bits) if mode=0 00529 // 14 | WnR - Write/not read. Should be 1 for channel 0 | 2) set nbuf to 0 |READ 0x21 instead !!! 00530 // 13 | depend. Should be set to 1 if needed to synchronize | | 15-00 | Same as written 00531 // | reading from SDRAM to writing from sensor | 00532 // 12 | should be 0 | 00533 // 11-00 | frame start address startAddr[18:7]. Addressed are | 00534 // | 16-bit words, low 7 bits are 0 (aligned to 128 word | 00535 // | page boundary | 00536 #define X313_WA_SDCH0_CTL1 0x21 // | Channel 0 (16 bit data sensor->SDRAM) | none | 31 | nbuf (buffer page number) 00537 //---353--- 00538 // 21 | | Channel 0 (16 bit data sensor->SDRAM) | none | 31-30 | nbuf[1:0] | 00539 // | 31-14 | not used | | 29-18 | ntileY[11:0] | 00540 // | 13-04 | nTileX[9:0]. For mode=0 nTileX[9:5] specifies number| | 17 | 0 | 00541 // | | of the last 8x16 block to read in a line. | | 16 | ntileX[4] | 00542 // | | Actual number of 8x16 blocks in a line is nTileX+1 | | 15-00 | Same as written | 00543 // | | For mode0 last 128x16 may be partial if | | | | 00544 // | | nTileX[9:5] != 0x1F | | | | 00545 // | 03-00 | startAddr[24:21] - used with other bits specified | | | | 00546 // | | at address 20 | | | | 00547 //---333--- 00548 // 21 | | Channel 0 (16 bit data sensor->SDRAM) | none | 31-30 | nbuf[1:0] | 00549 // | 31-14 | not used | | 29-18 | ntileY[11:0] | 00550 // | 13-04 | nTileX[9:0]. For mode=0 nTileX[9:5] specifies number| | 17 | 0 | 00551 // | | of the last 8x16 block to read in a line. | | 16 | ntileX[4] | 00552 // | | Actual number of 8x16 blocks in a line is nTileX+1 | | 15-00 | Same as written | 00553 // | | For mode0 last 128x16 may be partial if | | | | 00554 // | | nTileX[9:5] != 0x1F | | | | 00555 // | 03-00 | startAddr[23:20] - used with other bits specified | | | | 00556 // | | at address 20 | | | | 00557 //---313/323--- 00558 // 31-13 | not used | | | for ping-pong operation 00559 // 12-04 | nTileX[8:0]. For mode=0 nTileX[8:4] specify number | | 30-19 | tileY (12 bits) if mode=0 00560 // | of the last 8x16 block to read in a line. | | 18-14 | tileX (4 bits) if mode=0 00561 // | Actual number of 8x16 blocks in a line is nTileX+1 | | | 00562 // | For mode0 last 128x16 may be partial if | | 13-00 | Same as written 00563 // | nTileX[3:0] != 0xF | | | 00564 // 03-00 | startAddr[22:19] - used with other bits specified | | | 00565 // | ar address 00 | | | 00566 #define X313_WA_SDCH0_CTL2 0x22 00567 //---333--- 00568 // 22 | | Channel 0 (16 bit data sensor->SDRAM) | none | 31-30 | nbuf[1:0] | 00569 // | 31-12 | not used | | 29-18 | ntileY[11:0] | 00570 // | 11-00 | nTileY[11:0] - (for mode=0) - number of the last | | 17 | 0 | 00571 // | | line in in a frame. Total number of lines in | | 16-12 | ntileX[4:0] | 00572 // | | a frame is nTileY[11:0]+1 (mode=0) or | | 11-00 | Same as written | 00573 // | | (nTileY[11:0] & 12'hff0)+18 if mode =1 | | | | 00574 // | | (nTileY >> 4) +1 of rows of 18x9x16 (18x18x8) tiles | | | | 00575 //---313/323--- 00576 // Channel 0 (16 bit data sensor->SDRAM) | none | 31-16 | same as for address=20 00577 // 31-11 | not used | | 15-00 | same as written 00578 // 10-00 | nTileY[10:0] - (for mode=0) - number of the last | | | 00579 // | line in in a frame. Total number of lines in | | | 00580 // | a frame is nTileY[10:0]+1 (mode=0) or | | | 00581 // | (nTileY[10:0] & 11'h7f0)+16 if mode =1 | | | 00582 // | (nTileY >> 4) +1 of rows of 16x8x16 (16x16x8) tiles | | | 00583 #define X313_WA_SD_MANCMD 0x23 00584 00585 // | Manual command to SDRAM for initialization. Works | Perform one-cycle SDRAM manual | 31-16 | same as for address=20 00586 // | (and is recommended) if SDRAM is disabled (see re- | command by driving | 15-00 | same as written 00587 // | gister 27) | RAS,CAS,WE,BA[1:0],A[11/12:0] | | 00588 //---333/353 --- 00589 // | 31-18 | not used | | | | 00590 // | 17 | RAS | | | | 00591 // | 16 | CAS | | | | 00592 // | 15 | WE | | | | 00593 // | 14-13 | bank address [1:0] | | | | 00594 // | 12-00 | address[12:0] | | | | 00595 //---313/323--- 00596 // 31-16 | not used | according to data bits | | 00597 // 15-14 | 00 - write mode reg (RAS=L, CAS=L, WE=L) | | | 00598 // | 01 - refresh (RAS=L, CAS=L, WE=H) | | | 00599 // | 10 - precharge (RAS=L, CAS=H, WE=L) | | | 00600 // | 11 - nop (RAS=H, CAS=H, WE=H) | | | 00601 // 13-12 | bank address [1:0] | | | 00602 // 11-00 | address[11:0] | | | 00603 #define X313_WA_SDCH1_CTL0 0x24 00604 //---333--- 00605 // 24 | | Channel 1 (16 bit FPN data from SDRAM) | Initialize channel: | 31 | nbuf (buffer page number) | 00606 // | 31-16 | not used | 1) set address to startAddres | | for ping-pong operation | 00607 // | 15 | mode: 0 - 128x1 16-bit (or 256x1 bytes) | (word at address 01 with other | 30-20 | tileY (11 bits) if mode=0 | 00608 // | | 1 - 16x8 16 bit (or 16x16 bytes) | startAddress bits should be | 19-16 | tileX ( 4 bits) if mode=0 | 00609 // | | mode should be set to 0 for channel 0 | written earlier; | | | 00610 // | 14 | WnR - Write/not read. Should be 0 for channel 1 | 2) set nbuf to 0 | 15-00 | Same as written | 00611 // | 13 | depend. Should be set to 0 as FPN data is supposed | 3) start reading SDRAM as WnR | | | 00612 // | | to be always ready. | is 0 if channel 1 is enabled | | | 00613 // | 12 | not used | | | | 00614 // | 11-00 | frame start address startAddr[18:7]. Addressed are | | | | 00615 // | | 16-bit words, low 7 bits are 0 (aligned to 128 word | | | | 00616 // | | page boundary | | | | 00617 //---313/323--- 00618 // | Channel 1 (16 bit FPN data from SDRAM) | Initialize channel: | 31 | nbuf (buffer page number) 00619 // 31-16 | not used | 1) set address to startAddres | | for ping-pong operation 00620 // 15 | mode: 0 - 128x1 16-bit (or 256x1 bytes) | (word at address 01 with other | 30-20 | tileY (11 bits) if mode=0 00621 // | 1 - 16x8 16 bit (or 16x16 bytes) | startAddress bits should be | 19-16 | tileX ( 4 bits) if mode=0 00622 // | mode should be set to 0 for channel 0 | written earlier; | | 00623 // 14 | WnR - Write/not read. Should be 0 for channel 1 | 2) set nbuf to 0 | 15-00 | Same as written 00624 // 13 | depend. Should be set to 0 as FPN data is supposed | 3) start reading SDRAM as WnR | | 00625 // | to be always ready. | is 0 if channel 1 is enabled | | 00626 // 12 | not used | | | 00627 // 11-00 | frame start address startAddr[18:7]. Addressed are | | | 00628 // | 16-bit words, low 7 bits are 0 (aligned to 128 word | | | 00629 // | page boundary | | | 00630 #define X313_WA_SDCH1_CTL1 0x25 00631 //---333--- 00632 // 25 | | Channel 1 (16 bit FPN data from SDRAM) | none | 31-16 | same as for address=24 | 00633 // | 31-14 | not used | | 15-00 | same as written | 00634 // | 13-04 | nTileX[6:0]. For mode=0 nTileX[6:4] specify number | | | | 00635 // | | of the last 8x16 block to read in a line. | | | | 00636 // | | Actual number of 8x16 blocks in a line is nTileX+1 | | | | 00637 // | | For mode0 last 128x16 may be partial if | | | | 00638 // | | nTileX[3:0] != 0xF | | | | 00639 // | 03-00 | startAddr[22:19] - used with other bits specified | | | | 00640 // | | ar address 24 | | | | 00641 //---313/323--- 00642 // | Channel 1 (16 bit FPN data from SDRAM) | none | 31-16 | same as for address=24 00643 // 31-13 | not used | | 15-00 | same as written 00644 // 12-04 | nTileX[8:0]. For mode=0 nTileX[8:4] specify number | | | 00645 // | of the last 8x16 block to read in a line. | | | 00646 // | Actual number of 8x16 blocks in a line is nTileX+1 | | | 00647 // | For mode0 last 128x16 may be partial if | | | 00648 // | nTileX[3:0] != 0xF | | | 00649 // 03-00 | startAddr[22:19] - used with other bits specified | | | 00650 // | ar address 00 | | | 00651 #define X313_WA_SDCH1_CTL2 0x26 00652 //---333--- 00653 // 26 | | Channel 1 (16 bit FPN data from SDRAM) | none | 31-16 | same as for address=24 | 00654 // | 31-11 | not used | | 15-00 | same as written | 00655 // | 10-00 | nTileY[10:0] - (for mode=0) - number of the last | | | | 00656 // | | line in in a frame. Total number of lines in | | | | 00657 // | | a frame is nTileY[10:0]+1 (mode=0) or | | | | 00658 // | | (nTileY[10:0] & 11'h7f0)+16 if mode =1 | | | | 00659 // | | (nTileY >> 4) +1 of rows of 16x8x16 (16x16x8) tiles | | | | 00660 //---313/323--- 00661 // | Channel 1 (16 bit FPN data from SDRAM) | none | 31-16 | same as for address=24 00662 // 31-11 | not used | | 15-00 | same as written 00663 // 10-00 | nTileY[10:0] - (for mode=0) - number of the last | | | 00664 // | line in in a frame. Total number of lines in | | | 00665 // | a frame is nTileY[10:0]+1 (mode=0) or | | | 00666 // | (nTileY[10:0] & 11'h7f0)+16 if mode =1 | | | 00667 // | (nTileY >> 4) +1 of rows of 16x8x16 (16x16x8) tiles | | | 00668 00669 // with ETRAX FS there was a problem reading this register right after write to 0x20..0x2f range 00670 #define X313_WA_SD_MODE 0x27 00671 //---333--- 00672 //same as 313/323 00673 //---313/323--- 00674 // | Set SDRAM operation mode | change SDRAM mode by enabling | 31-16 | same as for address=24 00675 // 31-06 | not used | channels specified in data | 15-00 | same as written 00676 // 05 | enXfer[3] - enable SDRAM transfers for Channel 3 | | | 00677 // | CPU <-> SDRAM through PIO | | | 00678 // 04 | enXfer[2] - enable SDRAM transfers for Channel 2 | | | 00679 // | SDRAM -> (compressor) -> CPU through DMA | | | 00680 // 03 | enXfer[1] - enable SDRAM transfers for Channel 1 | | | 00681 // | SDRAM-> sensor data processor (FPN correction) | | | 00682 // 02 | enXfer[0] - enable SDRAM transfers for Channel 0 | | | 00683 // | sensor ->(FPN correction) ->SDRAM | | | 00684 // 01 | enRefresh - enable SDRAM automatic refresh as a | | | 00685 // | background process | | | 00686 // 00 | enSDRAM - enable SDRAM controller. If set to 0 | | | 00687 // | only manual commands are allowed (see register | | | 00688 // | at address 03) | | | 00689 #define X313_WA_SDCH2_CTL0 0x28 00690 //---333--- 00691 // 28 | | Channel 2 (8 bit data to JPEG encoder or just DMA) | Initialize channel: | 31 | nbuf (buffer page number) | 00692 // | 31-16 | not used | 1) set address to startAddres | | for ping-pong operation | 00693 // | 15 | mode: 0 - 128x1 16-bit (or 256x1 bytes) - N/A | (word at address 01 with other | 30-20 | tileY (11 bits) if mode=0 | 00694 // | | 1 - 16x8 16 bit (or 16x16 bytes) ****** | startAddress bits should be | 19-16 | tileX ( 4 bits) if mode=0 | 00695 // | | mode maybe set to either 0 for sequential access | written earlier; | | | 00696 // | | to raw data, or to 1 for JPEG 18x18 MCU access | | 30-24 | tileY ( 7 bits) if mode=1 | 00697 // | 14 | WnR - Write/not read. Should be 0 for channel 2 | 2) set nbuf to 0 | 23-16 | tileX ( 8 bits) if mode=1 | 00698 // | 13 | depend. May be set to 1 to force encoder/DMA wait | 3) start reading SDRAM as WnR | | | 00699 // | | for sensor data available. Should work correctly | is 0 if channel 2 is enabled | 15-00 | Same as written | 00700 // | | for sequentional write and tiled read. | | | | 00701 // | 12 | not used | | | | 00702 // | 11-00 | frame start address startAddr[19:8]. Addressed are | | | | 00703 // | | 16-bit words, low 8 bits are 0 (aligned to 256 word | | | | 00704 // | | page boundary | | | | 00705 //---313/323--- 00706 // | Channel 2 (8 bit data to JPEG encoder or just DMA) | Initialize channel: | 31 | nbuf (buffer page number) 00707 // 31-16 | not used | 1) set address to startAddres | | for ping-pong operation 00708 // 15 | mode: 0 - 128x1 16-bit (or 256x1 bytes) | (word at address 01 with other | 30-20 | tileY (11 bits) if mode=0 00709 // | 1 - 16x8 16 bit (or 16x16 bytes) | startAddress bits should be | 19-16 | tileX ( 4 bits) if mode=0 00710 // | mode maybe set to either 0 for sequential access | written earlier; | | 00711 // | to raw data, or to 1 for JPEG 16x16 MCU access | | 30-24 | tileY ( 7 bits) if mode=1 00712 // 14 | WnR - Write/not read. Should be 0 for channel 2 | 2) set nbuf to 0 | 23-16 | tileX ( 8 bits) if mode=1 00713 // 13 | depend. May be set to 1 to force encoder/DMA wait | 3) start reading SDRAM as WnR | | 00714 // | for sensor data available. Should work correctly | is 0 if channel 2 is enabled | 15-00 | Same as written 00715 // | for sequentional write and tiled read. | | | 00716 // 12 | not used | | | 00717 // 11-00 | frame start address startAddr[18:7]. Addressed are | | | 00718 // | 16-bit words, low 7 bits are 0 (aligned to 128 word | | | 00719 // | page boundary | | | 00720 #define X313_WA_SDCH2_CTL1 0x29 00721 //---333--- 00722 // 29 | | Channel 2 (8 bit data to JPEG encoder or just DMA) | none | 31 | nbuf[1] | 00723 // | 31-14 | not used | | 30 | nbuf[0] | 00724 // | 13-04 | nTileX[9:0]. Mode is supposed to be 1 | | 29-22 | ntyleY[11:4] | 00725 // | | Actual number of 8x16 blocks in a line is nTileX+1 | | 21-16 | ntileX[9:4] | 00726 // | | | | | | 00727 // | 03-00 | startAddr[23:20] - used with other bits specified | | | | 00728 // | | at address 28 | | | | 00729 //---313/323--- 00730 // | Channel 2 (8 bit data to JPEG encoder or just DMA) | none | 31-16 | same as for address=28 00731 // 31-13 | not used | | 15-00 | same as written 00732 // 12-04 | nTileX[8:0]. For mode=0 nTileX[8:4] specify number | | | 00733 // | of the last 8x16 block to read in a line. | | | 00734 // | Actual number of 8x16 blocks in a line is nTileX+1 | | | 00735 // | For mode0 last 128x16 may be partial if | | | 00736 // | nTileX[3:0] != 0xF | | | 00737 // 03-00 | startAddr[22:19] - used with other bits specified | | | 00738 // | ar address 00 | | | 00739 #define X313_WA_SDCH2_CTL2 0x2a 00740 //---333--- 00741 // 2a | | Channel 2 (8 bit data to JPEG encoder or just DMA) | none | 31 | nbuf[1] | 00742 // | 31-12 | not used | | 30 | nbuf[0] | 00743 // | 11-00 | nTileY[11:0] - (for mode=0) - number of the last | | 29-22 | ntyleY[11:4] | 00744 // | | line in in a frame. Total number of lines in | | 21-12 | ntileX[9:0] | 00745 // | | a frame is nTileY[10:0]+1 (mode=0) or | | 11-00 | Same as written | 00746 // | | (nTileY[10:0] & 11'h7f0)+16 if mode =1 | | | | 00747 // | | (nTileY >> 4) +1 of rows of 16x8x16 (16x16x8) tiles | | | | 00748 //---313/323--- 00749 // | Channel 2 (8 bit data to JPEG encoder or just DMA) | none | 31-16 | same as for address=28 00750 // 31-11 | not used | | 15-00 | same as written 00751 // 10-00 | nTileY[10:0] - (for mode=0) - number of the last | | | 00752 // | line in in a frame. Total number of lines in | | | 00753 // | a frame is nTileY[10:0]+1 (mode=0) or | | | 00754 // | (nTileY[10:0] & 11'h7f0)+16 if mode =1 | | | 00755 // | (nTileY >> 4) +1 of rows of 16x8x16 (16x16x8) tiles | | | 00756 #define X313_WA_SDCH3_CTL0 0x2c 00757 //---333--- 00758 // 2c | | Channel 3 (CPU PIO <-> SDRAM) | Initialize channel: | (mode 0) | 00759 // | 31-16 | not used | 1) set address to startAddres | 31-30 | nbuf[1:0] | 00760 // | 15 | mode: 0 - 256x1 16-bit (or 512x1 bytes) | (word at address 01 with other | 29-18 | ntileY[11:0] | 00761 // | | 1 - 18x9 16 bit (or 18x18 bytes) | startAddress bits should be | 17-16 | ntileX[8:7] | 00762 // | | mode should be set to 0 for channel 0 | written earlier; | | | 00763 // | 14 | WnR - Write/not read. Should be 1 for channel 0 | 2) set nbuf[1:0] to 0 | 15-00 | Same as written | 00764 // | 13 | depend. Should be set to 1 if needed to synchronize | | | | 00765 // | | reading from SDRAM to writing from sensor | | | | 00766 // | 12 | not used | | | | 00767 // | 11-00 | frame start address startAddr[19:8]. Addressed are | | | | 00768 // | | 16-bit words, low 8 bits are 0 (aligned to 256 word | | | | 00769 // | | page boundary | | | | 00770 //---313/323--- 00771 // | Channel 3 (CPU PIO <-> SDRAM) | Initialize channel: | 31 | nbuf (buffer page number) 00772 // 31-16 | not used | 1) set address to startAddres | | for ping-pong operation 00773 // 15 | mode: 0 - 128x1 16-bit (or 256x1 bytes) | (word at address 01 with other | 30-20 | tileY (11 bits) if mode=0 00774 // | 1 - 16x8 16 bit (or 16x16 bytes) | startAddress bits should be | 19-16 | tileX ( 4 bits) if mode=0 00775 // | mode maybe set to either 0 for sequential access | written earlier; | | 00776 // | to raw data, or to 1 16x16x8 tiled | | 30-24 | tileY ( 7 bits) if mode=1 00777 // 14 | WnR - Write/not read. May be set to any value for | 2) set nbuf to 0 | 23-16 | tileX ( 8 bits) if mode=1 00778 // | Channel 3 - it works both ways | | | 00779 // 13 | depend. May be set to 1 to force the channel wait | 3) start reading SDRAM if WnR | | 00780 // | for sensor data available. (Read through status) | is 0 and channel 3 is enabled | 15-00 | Same as written 00781 // 12 | read DC coimponents instead of SDRAM | | | 00782 // 11-00 | frame start address startAddr[18:7]. Addressed are | | | 00783 // | 16-bit words, low 7 bits are 0 (aligned to 128 word | | | 00784 // | page boundary | | | 00785 #define X313_WA_SDCH3_CTL1 0x2d 00786 //---333--- 00787 // 2d | | Channel 3 (CPU PIO <-> SDRAM) | none | 31-30 | nbuf[1:0] | 00788 // | 31-14 | not used | | 29-18 | ntileY[11:0] | 00789 // | 13-04 | nTileX[9:0]. For mode=0 nTileX[9:5] specifies number| | 17 | 0 | 00790 // | | of the 8x16 blocks to read in a line. | | 16 | ntileX[4] | 00791 // | | Actual number of 8x16 blocks in a line is nTileX+1 | | 15-00 | Same as written | 00792 // | | For mode0 last 256x16 may be partial if | | | | 00793 // | | nTileX[9:5] != 0x00 | | | | 00794 // | 03-00 | startAddr[23:20] - used with other bits specified | | | | 00795 // | | at address 2c | | | | 00796 //---313/323--- 00797 // | Channel 3 (CPU PIO <-> SDRAM) | none | 31-16 | same as for address=2c 00798 // 31-13 | not used | | 15-00 | same as written 00799 // 12-04 | nTileX[8:0]. For mode=0 nTileX[8:4] specify number | | | 00800 // | of the last 8x16 block to read in a line. | | | 00801 // | Actual number of 8x16 blocks in a line is nTileX+1 | | | 00802 // | For mode0 last 128x16 may be partial if | | | 00803 // | nTileX[3:0] != 0xF | | | 00804 // 03-00 | startAddr[22:19] - used with other bits specified | | | 00805 // | ar address 00 | | | 00806 #define X313_WA_SDCH3_CTL2 0x2e 00807 //---333--- 00808 // 2e | | Channel 3 (CPU PIO <-> SDRAM) | none | 31-30 | nbuf[1:0] | 00809 // | 31-12 | not used | | 29-18 | ntileY[11:0] | 00810 // | 11-00 | nTileY[11:0] - (for mode=0) - number of the last | | 17 | 0 | 00811 // | | line in in a frame. Total number of lines in | | 16-12 | ntileX[4:0] | 00812 // | | a frame is nTileY[11:0]+1 (mode=0) or | | 11-00 | Same as written | 00813 // | | (nTileY[11:0] & 12'hff0)+18 if mode =1 | | | | 00814 // | | (nTileY >> 4) +1 of rows of 18x9x16 (18x18x8) tiles | | | | 00815 //---313/323--- 00816 // | Channel 3 (CPU PIO <-> SDRAM) | none | 31-16 | same as for address=2c 00817 // 31-11 | not used | | 15-00 | same as written 00818 // 10-00 | nTileY[10:0] - (for mode=0) - number of the last | | | 00819 // | line in in a frame. Total number of lines in | | | 00820 // | a frame is nTileY[10:0]+1 (mode=0) or | | | 00821 // | (nTileY[10:0] & 11'h7f0)+16 if mode =1 | | | 00822 // | (nTileY >> 4) +1 of rows of 16x8x16 (16x16x8) tiles | | | 00823 #define X313_WA_SDPIO_NEXT 0x2f 00824 //---333--- 00825 // similar to 313/333 but will open access to next 128x32bit page, resets address inside page 00826 //---313/323--- 00827 // | Channel 3 (CPU PIO <-> SDRAM) | Next page (8x32 bit window) | 31-16 | same as for address=2c 00828 // 31-00 | not used | for CPU PIO access. Check | 15-00 | same as written 00829 // | | status bit to see ifbuffer is | | 00830 // | | ready | | 00831 #define X313_WA_SD_PIOWIN 0x30 00832 //---333--- 00833 // read/write SDRAM data (channel3), address inside a 128x32bit page is reset when programming channel3 (write to X313_WA_SDCH3_CTL0) 00834 // and switching to the new page (X313_WA_SDPIO_NEXT). After each write address is incremented, fow reads it is incremented only 00835 // when using port_csp4_addr[], not port_csp0_addr[]! (that access should be configured with 1 early wait state to make OE signal to pulse) 00836 // read from X313_WA_SD_PIOWIN has 1 access latency 00837 //---313/323--- 00838 // | write SDRAM data through 8x32 window | | Read SDRAM data through 8x32 00839 00840 00841 /* control register fields */ 00842 //#define X313__TRIGLOW__BITNM 0 // 1 - force TRIG input low (0 - normal input) 00843 //#define X313__TRIGLOW__WIDTH 1 00844 00845 /* 00846 | 00 | | Control register | | | DMA data (will change | 00847 | | | | | | by DACK pulse) | 00848 | | 31 | cb_clken | | | Enable sens. clock output | 00849 | | 30-28 | autofocus (lower freq. number to count) | | | | 00850 | | 27-24 | pixel clock source: | | | | 00851 | | | 0 - external clock (clk1) | | | | 00852 | | | 1 - clk0/1 | | | | 00853 | | | 2 - clk0/1.5 | | | | 00854 | | | 3 - clk0/2 | | | | 00855 | | | ... | | | | 00856 | | | 15 - clk0/8 | | | | 00857 | | 23 | not used | | | | 00858 | | 22 | sda1_en | | | | 00859 | | 21 | sda1_do | | | | 00860 | | 20 | scl1_en | | | | 00861 | | 19 | scl1_do | | | | 00862 | | 18 | sda0_en -> sa | | | | 00863 | | 17 | sda0_do -> sb | | | | 00864 | | 16 | scl0_en -> not used | | | | 00865 | | 15 | scl0_do -> not used | | | | 00866 | | 14 | cb_xrst | | | | 00867 | | 13 | mrst -> not used | | | | 00868 | | 12 | cb_exppol | | | | 00869 | | 11 | cb_exp | | | | 00870 | | | | | | | 00871 | | 10 | aro-> not used | | | | 00872 | | 9 | arst-> not used | | | | 00873 | | 8 | xt_pol | | | | 00874 // straighten that later 00875 | | 6 | zoran (0 - Kodak, 1 - Zoran & Micron)-> not used | | | | 00876 | | 5 | delay ihact-> not used | | | | 00877 00878 | | 4 | FillFactory (also inverts mrst)-> not used | | | | 00879 | | 3 | AUXCLK (0-1, 1- 1) | | | | 00880 | | 2 | (not impl. yet) output clk(?) to AUXCLK | | | | 00881 00882 */ 00883 00884 // valid for model 323 00885 #define X313__X323SA__BITNM 18 // 00886 #define X313__X323SA__WIDTH 1 00887 00888 #define X313__X323SB__BITNM 17 // 00889 #define X313__X323SB__WIDTH 1 00890 00891 00892 #define X313__KAI11000__BITNM 1 // no fpga meaning yet, just shadow 00893 #define X313__KAI11000__WIDTH 1 00894 00895 00896 #define X313__BAYER_PHASE__BITNM 1 // move to 313 branch too 00897 #define X313__BAYER_PHASE__WIDTH 2 00898 00899 00900 // INVERTCLOCK - remove later, use DCM 00901 #define X313__AUXCLK__BITNM 3 00902 #define X313__AUXCLK__WIDTH 1 00903 00904 #define X313__FILLFACTORY__BITNM 4 00905 #define X313__FILLFACTORY__WIDTH 1 00906 #define X313__DLYHOR__BITNM 5 00907 #define X313__DLYHOR__WIDTH 1 00908 #define X313__NEGRST__BITNM 6 00909 #define X313__NEGRST__WIDTH 1 00910 00911 #define X313__SKIPLINEL__BITNM 7 00912 #define X313__SKIPLINE__WIDTH 1 00913 00914 00915 #define X313__XT_POL__BITNM 8 00916 #define X313__XT_POL__WIDTH 1 00917 #define X313__ARST__BITNM 9 00918 #define X313__ARST__WIDTH 1 00919 #define X313__ARO__BITNM 10 00920 #define X313__ARO__WIDTH 1 00921 00922 // for 5MPix set - old sensors, reset - new ones 00923 #define X313__CNVEN__BITNM 11 00924 #define X313__CNVEN__WIDTH 1 00925 00926 // bits 11,12 below not used in 353 00927 #define X313__EXP__BITNM 11 00928 #define X313__EXP__WIDTH 1 00929 #define X313__EXPPOL__BITNM 12 00930 #define X313__EXPPOL__WIDTH 1 00931 00932 #define X313__TRIGSRC__BITNM 12 00933 #define X313__TRIGSRC__WIDTH 1 00934 00935 00936 // 353 only (use TRIGGER signal on ARO output) 00937 #define X313__SENSTRIGEN__BITNM 12 00938 #define X313__SENSTRIGEN__WIDTH 1 00939 00940 // use start of trigger as a timestamp (in async mode to prevent timestamp jitter) 00941 #define X313__EARLYTRIG__BITNM 14 00942 #define X313__EARLYTRIG__WIDTH 1 00943 00944 00945 #define X313__MRST__BITNM 13 00946 #define X313__MRST__WIDTH 1 00947 00948 // bit 14 below not used in 353 00949 #define X313__XRST__BITNM 14 00950 #define X313__XRST__WIDTH 1 00951 00952 #define X313__SCL0__BITNM 15 00953 #define X313__SCL0__WIDTH 1 00954 #define X313__SCL0_EN__BITNM 16 00955 #define X313__SCL0_EN__WIDTH 1 00956 #define X313__SDA0__BITNM 17 00957 #define X313__SDA0__WIDTH 1 00958 #define X313__SDA0_EN__BITNM 18 00959 #define X313__SDA0_EN__WIDTH 1 00960 00961 //DCLKMODE - 0 - DCLK - clock to sensor, 1 - DCLK - input of conposite sync (from 10347) 00962 #define X313__DCLKMODE__BITNM 19 00963 #define X313__DCLKMODE__WIDTH 1 00964 00965 //PXD14 - 1 - 14-bit data from sensor 00966 #define X313__PXD14__BITNM 20 00967 #define X313__PXD14__WIDTH 1 00968 00969 00970 00971 // SCL1/SDA1 not implemented in 353 00972 #define X313__SCL1__BITNM 19 00973 #define X313__SCL1__WIDTH 1 00974 #define X313__SCL1_EN__BITNM 20 00975 #define X313__SCL1_EN__WIDTH 1 00976 #define X313__SDA1__BITNM 21 00977 #define X313__SDA1__WIDTH 1 00978 #define X313__SDA1_EN__BITNM 22 00979 #define X313__SDA1_EN__WIDTH 1 00980 #define X313__SOFTRST__BITNM 23 00981 #define X313__SOFTRST__WIDTH 1 00982 00983 // source of pixel clock. Now 0 - internal (CLK1), 1,2,3 - external (bpf) 00984 00985 #define X313__PCLKSRC__BITNM 24 00986 #define X313__PCLKSRC__WIDTH 2 00987 00988 00989 #define X313__HFCOMP__BITNM 28 00990 #define X313__HFCOMP__WIDTH 3 00991 00992 00993 #define X313__CLKEN__BITNM 31 00994 #define X313__CLKEN__WIDTH 1 00995 00996 #define X313__HACT_PHASE__BITNM 21 00997 #define X313__HACT_PHASE__WIDTH 2 00998 00999 01000 01001 #define X313_MASK(x) (( (1 << X313__##x##__WIDTH)-1) << X313__##x##__BITNM) 01002 #define X313_BITS(x,y) (((y) & ((1 << X313__##x##__WIDTH)-1)) << X313__##x##__BITNM) 01003 01004 01005 // preserved 323 - probably not needed 01006 #ifdef CONFIG_ETRAX_ELPHEL353 01007 #define IS_KAI11000 (ccam_cr_shadow & X313_MASK(PXD14)) 01008 #else 01009 #define IS_KAI11000 (ccam_cr_shadow & X313_MASK(KAI11000)) 01010 #endif 01011 01012 /*!******************************************************************************************************* 01013 *! Moved all references to FPGA access to memory-control registers here to simplify code maitenance 01014 *! when FPGA changes. 01015 *! 01016 *! Split SDARM channel initailization in 3 macros 01017 *! X313_PREINIT_SDCHAN(num,mode,wnr,dep,sa,ntilex,ntiley) - writes two (of 3) registers (not yet starting the channel) 01018 *! returns value foo the 3-rd (command) register 01019 *! X313_PREINIT_SDCHAN(num,cmd) - writes the channel command register, starting it 01020 *! waits 2 cycles after (if ETRAX FS) to make next reads safe 01021 *! X313_INIT_SDCHAN(num,mode,wnr,dep,sa,ntilex,ntiley) - combination of the 2 above, works as before 01022 *! 01023 *!/ added X3X3_AFTERWRITE to be able to read FPGA after that macro (w/o -= failed in ETRAX FS) 01024 */ 01025 01026 01027 01028 #ifdef CONFIG_ETRAX_ELPHEL353 01029 // now for photo-finish mode set mode=1, wnr=1 (it will still be read for channel2) 01030 #if 0 01031 #define X313_PREINIT_SDCHAN(num,mode,wnr,dep,sa,ntilex,ntiley) \ 01032 ((port_csp0_addr[X313_WA_SDCH0_CTL0+1+((num)<<2)] = (((ntilex) & 0x3ff) << 4) | (((sa) >> 21) & 0xf)), \ 01033 (port_csp0_addr[X313_WA_SDCH0_CTL0+2+((num)<<2)] = 0x8000 | ((ntiley) & 0xfff)), \ 01034 (((mode) & 1) << 15) | (((wnr) & 1) << 14) | (((dep) & 1) << 13) | (((sa) >> 8) & 0x1fff)) 01035 #endif 01036 #define X313_PREINIT_SDCHAN(num,mode,wnr,dep,sa,ntilex,ntiley) \ 01037 ((port_csp0_addr[X313_WA_SDCH0_CTL0+1+((num)<<2)] = (0x8000 | (((ntilex) & 0x3ff) << 4) | (((sa) >> 21) & 0xf))), \ 01038 (port_csp0_addr[X313_WA_SDCH0_CTL0+2+((num)<<2)] = ((ntiley) & 0xfff)), \ 01039 (((mode) & 1) << 15) | (((wnr) & 1) << 14) | (((dep) & 1) << 13) | (((sa) >> 8) & 0x1fff)) 01040 // 0x8000 is used just to mark it is programmed - no hardware meaning 01041 #else 01042 #ifdef CONFIG_ETRAX_333 01043 #define X313_PREINIT_SDCHAN(num,mode,wnr,dep,sa,ntilex,ntiley) \ 01044 ((port_csp0_addr[X313_WA_SDCH0_CTL0+1+((num)<<2)] = (((ntilex) & 0x3ff) << 4) | (((sa) >> 20) & 0xf)), \ 01045 (port_csp0_addr[X313_WA_SDCH0_CTL0+2+((num)<<2)] = 0x8000 | ((ntiley) & 0xfff)), \ 01046 (((mode) & 1) << 15) | (((wnr) & 1) << 14) | (((dep) & 1) << 13) | (((sa) >> 8) & 0xfff)) 01047 // 0x8000 is used just to mark it is programmed - no hardware meaning 01048 #else 01049 #define X313_PREPREINIT_SDCHAN(num,mode,wnr,dep,sa,ntilex,ntiley) \ 01050 ((port_csp0_addr[X313_WA_SDCH0_CTL0+1+((num)<<2)] = (((ntilex) & 0x1ff) << 4) | (((sa) >> 19) & 0xf)), \ 01051 (port_csp0_addr[X313_WA_SDCH0_CTL0+2+((num)<<2)] = 0x8000 | ((ntiley) & 0xfff)), \ 01052 (((mode) & 1) << 15) | (((wnr) & 1) << 14) | (((dep) & 1) << 13) | (((sa) >> 7) & 0xfff)) 01053 // 0x8000 is used just to mark it is programmed - no hardware meaning 01054 #endif 01055 #endif 01056 01057 01058 #ifdef CONFIG_ETRAX_ELPHEL353 01059 #define X313_POSTINIT_SDCHAN(num,cmd) {port_csp0_addr[X313_WA_SDCH0_CTL0+0+((num)<<2)] = cmd; X3X3_AFTERWRITE} 01060 #else 01061 #define X313_POSTINIT_SDCHAN(num,cmd) {port_csp0_addr[X313_WA_SDCH0_CTL0+0+((num)<<2)] = cmd } 01062 #endif 01063 01064 #define X313_INIT_SDCHAN(num,mode,wnr,dep,sa,ntilex,ntiley) \ 01065 {X313_POSTINIT_SDCHAN ( num, X313_PREINIT_SDCHAN ( num,mode,wnr,dep,sa,ntilex,ntiley ))} 01066 01067 01068 01069 #if 0 01070 #ifdef CONFIG_ETRAX_ELPHEL353 01071 // now for photo-finish mode set mode=1, wnr=1 (it will still be read for channel2) 01072 #if 1 01073 #define X313_INIT_SDCHAN(num,mode,wnr,dep,sa,ntilex,ntiley) \ 01074 {port_csp0_addr[X313_WA_SDCH0_CTL0+1+((num)<<2)] = (((ntilex) & 0x3ff) << 4) | (((sa) >> 21) & 0xf); \ 01075 port_csp0_addr[X313_WA_SDCH0_CTL0+2+((num)<<2)] = 0x8000 | ((ntiley) & 0xfff); \ 01076 port_csp0_addr[X313_WA_SDCH0_CTL0+0+((num)<<2)] = (((mode) & 1) << 15) | (((wnr) & 1) << 14) | (((dep) & 1) << 13) | (((sa) >> 8) & 0x1fff); \ 01077 X3X3_AFTERWRITE ; \ 01078 printk ("%x %x %x - %x %x %x\r\n", (int) ((((ntilex) & 0x3ff) << 4) | (((sa) >> 21) & 0xf)), \ 01079 (int) (0x8000 | ((ntiley) & 0xfff)), \ 01080 (int) ((((mode) & 1) << 15) | (((wnr) & 1) << 14) | (((dep) & 1) << 13) | (((sa) >> 8) & 0x1fff)), \ 01081 (int) port_csp0_addr[X313_WA_SDCH0_CTL0+1+((num)<<2)], \ 01082 (int) port_csp0_addr[X313_WA_SDCH0_CTL0+2+((num)<<2)], \ 01083 (int) port_csp0_addr[X313_WA_SDCH0_CTL0+0+((num)<<2)]);} 01084 01085 #else 01086 #define X313_INIT_SDCHAN(num,mode,wnr,dep,sa,ntilex,ntiley) \ 01087 {port_csp0_addr[X313_WA_SDCH0_CTL0+1+((num)<<2)] = (((ntilex) & 0x3ff) << 4) | (((sa) >> 21) & 0xf); \ 01088 port_csp0_addr[X313_WA_SDCH0_CTL0+2+((num)<<2)] = 0x8000 | ((ntiley) & 0xfff); \ 01089 port_csp0_addr[X313_WA_SDCH0_CTL0+0+((num)<<2)] = (((mode) & 1) << 15) | (((wnr) & 1) << 14) | (((dep) & 1) << 13) | (((sa) >> 8) & 0x1fff); \ 01090 X3X3_AFTERWRITE} 01091 #endif 01092 // 0x8000 is used just to mark it is programmed - no hardware meaning 01093 #else 01094 #ifdef CONFIG_ETRAX_333 01095 #define X313_INIT_SDCHAN(num,mode,wnr,dep,sa,ntilex,ntiley) \ 01096 {port_csp0_addr[X313_WA_SDCH0_CTL0+1+((num)<<2)] = (((ntilex) & 0x3ff) << 4) | (((sa) >> 20) & 0xf); \ 01097 port_csp0_addr[X313_WA_SDCH0_CTL0+2+((num)<<2)] = 0x8000 | ((ntiley) & 0xfff); \ 01098 port_csp0_addr[X313_WA_SDCH0_CTL0+0+((num)<<2)] = (((mode) & 1) << 15) | (((wnr) & 1) << 14) | (((dep) & 1) << 13) | (((sa) >> 8) & 0xfff);} 01099 // 0x8000 is used just to mark it is programmed - no hardware meaning 01100 #else 01101 #define X313_INIT_SDCHAN(num,mode,wnr,dep,sa,ntilex,ntiley) \ 01102 {port_csp0_addr[X313_WA_SDCH0_CTL0+1+((num)<<2)] = (((ntilex) & 0x1ff) << 4) | (((sa) >> 19) & 0xf); \ 01103 port_csp0_addr[X313_WA_SDCH0_CTL0+2+((num)<<2)] = 0x8000 | ((ntiley) & 0xfff); \ 01104 port_csp0_addr[X313_WA_SDCH0_CTL0+0+((num)<<2)] = (((mode) & 1) << 15) | (((wnr) & 1) << 14) | (((dep) & 1) << 13) | (((sa) >> 7) & 0xfff);} 01105 // 0x8000 is used just to mark it is programmed - no hardware meaning 01106 #endif 01107 #endif 01108 #endif 01109 01110 01111 01112 #define X313_CHN_EN(x) {X3X3_AFTERWRITE ; port_csp0_addr[X313_WA_SD_MODE] |= ((4 << ((x)& 3)) | 3); } // added |3 so SDRAM will be enabled too 01113 #define X313_CHN_DIS(x) {X3X3_AFTERWRITE ; port_csp0_addr[X313_WA_SD_MODE] &= ~(4 << ((x)& 3)); } 01114 #define X313_CHN_DISALL {X3X3_AFTERWRITE ; port_csp0_addr[X313_WA_SD_MODE] &= 3 ; } 01115 #define X313_SDRAM_OFF {port_csp0_addr[X313_WA_SD_MODE]=0;} // no need to wait here 01116 #define X313_SDRAM_ON {port_csp0_addr[X313_WA_SD_MODE]=3;} // no need to wait here - will disable all channels but refresh 01117 #define X313_IS_SDRAM_ON (port_csp0_addr[X313_WA_SD_MODE],((port_csp0_addr[X313_WA_SD_MODE] & 3)==3)) // first - dummy read 01118 #define X313_CHN0_BOUND (port_csp0_addr[X313_WA_SDCH2_CTL0],(port_csp0_addr[X313_WA_SDCH2_CTL0] & 0x2000)) 01119 01120 #define X313_XFERCNTR (port_csp0_addr[X313__RA__XFERCNTR],port_csp0_addr[X313__RA__XFERCNTR]) 01121 #define X313_HIGHFREQ (port_csp0_addr[X313__RA__HIGHFREQ],port_csp0_addr[X313__RA__HIGHFREQ]) 01122 #define X313_IRQSTATE (port_csp0_addr[0x11],port_csp0_addr[0x11]) 01123 #define X313_IOPINS (port_csp0_addr[X313__RA__IOPINS],port_csp0_addr[X313__RA__IOPINS]) 01124 01125 01126 01127 // channel 0 was programmed (will set dummy bit 15) - model 333 01128 // channel 0 was programmed (will set dummy bit 15) - model 313 01129 #if 0 01130 #define X313_CHN0_USED ( (port_csp0_addr[X313_WA_SDCH0_CTL1]& 0xffff), \ 01131 ((port_csp0_addr[X313_WA_SDCH0_CTL1] | (port_csp0_addr[X313_WA_SDCH0_CTL2])) & 0xffff) ) 01132 01133 #define X313_CHN0_SET_USED { port_csp0_addr[X313_WA_SDCH0_CTL1]=0x8000; port_csp0_addr[X313_WA_SDCH0_CTL2]=0x8000; } 01134 #define X313_CHN0_SET_UNUSED { port_csp0_addr[X313_WA_SDCH0_CTL1]=0; port_csp0_addr[X313_WA_SDCH0_CTL2]=0; } 01135 #endif 01137 #define X313_CHN0_USED ( (port_csp0_addr[X313_WA_SDCH0_CTL1]& 0xffff), \ 01138 (port_csp0_addr[X313_WA_SDCH0_CTL1] & 0xffff) ) 01139 01140 #define X313_CHN0_SET_USED { port_csp0_addr[X313_WA_SDCH0_CTL1]=0x8000; } 01141 #define X313_CHN0_SET_UNUSED { port_csp0_addr[X313_WA_SDCH0_CTL1]=0; } 01142 01143 01144 #define X313_SET_FPGA_TIME(x,y) { port_csp0_addr[X313_WA_RTC_USEC]= ( y ); port_csp0_addr[X313_WA_RTC_SEC]= ( x ); } 01145 #define X313_GET_FPGA_TIME(x,y) { port_csp0_addr[X313_WA_RTC_LATCH]= 0; X3X3_AFTERWRITE ; x = port_csp0_addr[X313_WA_RTC_SEC]; y = port_csp0_addr[X313_WA_RTC_USEC];} 01146 #define X313_GET_FPGA_SECONDS(x) { port_csp0_addr[X313_WA_RTC_LATCH]= 0; X3X3_AFTERWRITE ; x = port_csp0_addr[X313_WA_RTC_SEC]} 01147 01148 01149 01150 // As I will use application, not driver to access frame memory, I'll put here SDRAM memory map 01151 // The window size is designed to fit 1280x1024x16 - FPN, twice as much for image 01152 #define X313_MAP_FPN 0 01153 #ifdef CONFIG_ETRAX_ELPHEL353 01154 #define X313_SDRAM_SIZE 0x4000000 01155 #define X313_MAXWIDTH 4096 // multiple of 128 01156 #define X313_MAXHEIGHT 4096 // multiple of 16 (actual - 2720) 01157 #define X313_MAP_FRAME ((X313_MAP_FPN) + (X313_MAXWIDTH) * (X313_MAXHEIGHT)) 01158 #define X313_MARGINS 4 01159 #endif 01160 #ifdef CONFIG_ETRAX_333 01161 #define X313_SDRAM_SIZE 0x2000000 01162 #define X313_MAXWIDTH 4096 // multiple of 128 01163 #define X313_MAXHEIGHT 4096 // multiple of 16 (actual - 2720) 01164 #define X313_MAP_FRAME ((X313_MAP_FPN) + (X313_MAXWIDTH) * (X313_MAXHEIGHT)) 01165 #define X313_MARGINS 4 01166 #endif 01167 #ifdef CONFIG_ETRAX_323 01168 #define X313_SDRAM_SIZE 0x1000000 01169 #define X313_MAP_FRAME 0 01170 #define X313_MAXWIDTH 4096 // multiple of 128 01171 #define X313_MAXHEIGHT 4096 // multiple of 16 (actual - 2720) 01172 #define X323_ACQUIRE 0x14 01173 #define X313_MARGINS 2 01174 #endif 01175 #ifdef CONFIG_ETRAX_313 01176 #define X313_SDRAM_SIZE 0x1000000 01177 #define X313_MAXWIDTH 2048 // multiple of 128 01178 #define X313_MAXHEIGHT 1536 // multiple of 16 01179 #define X313_MAP_FRAME ((X313_MAP_FPN) + (X313_MAXWIDTH) * (X313_MAXHEIGHT)) 01180 #define X313_MARGINS 2 01181 #endif 01182 01183
1.5.1