apps/fpcf/fpcf.c

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/*!***************************************************************************
*! FILE NAME  : fpcf.c
*! DESCRIPTION: A big set of different FPGA-related commands
*! Copyright (C) 2002-2007 Elphel, Inc.
*! -----------------------------------------------------------------------------**
*!  This program is free software: you can redistribute it and/or modify
*!  it under the terms of the GNU General Public License as published by
*!  the Free Software Foundation, either version 3 of the License, or
*!  (at your option) any later version.
*!
*!  This program is distributed in the hope that it will be useful,
*!  but WITHOUT ANY WARRANTY; without even the implied warranty of
*!  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
*!  GNU General Public License for more details.
*!
*!  You should have received a copy of the GNU General Public License
*!  along with this program.  If not, see <http://www.gnu.org/licenses/>.
*! -----------------------------------------------------------------------------**
*!  $Log: fpcf.c,v $
*!  Revision 1.7  2008/08/01 23:52:44  spectr_rain
*!  add result=OK string to output of SDRAM phase settings and SDRAM memory test
*!
*!  Revision 1.6  2008/04/29 06:24:06  elphel
*!  used strtoll() instead of strtol to handle unsigned long >=0x7fffffff
*!
*!  Revision 1.5  2008/04/09 19:46:59  elphel
*!  added fflush
*!
*!  Revision 1.4  2008/04/09 19:35:08  elphel
*!  removed "test error"
*!
*!  Revision 1.3  2008/04/09 19:33:07  elphel
*!  added system memory test, more wait state registers
*!
*!  Revision 1.2  2008/01/25 07:13:01  elphel
*!  typo
*!
*!  Revision 1.1.1.1  2007/09/30 03:20:25  elphel
*!  This is a fresh tree based on elphel353-2.10
*!
*!  Revision 1.5  2007/09/30 03:20:25  elphel
*!  fixed comment typo
*!
*!  Revision 1.4  2007/09/16 06:15:42  elphel
*!  Just debug info (disabled by #define) to troubleshoot sctl.cgi
*!
*!  Revision 1.3  2007/08/17 12:12:22  spectr_rain
*!  switch to GPL3 license
*!
*!  Revision 1.2  2007/07/10 08:25:44  spectr_rain
*!  *** empty log message ***
*!
*!  Revision 1.3  2007/04/17 21:37:16  elphel
*!  added short output for "fpcf -c <bit_number>"
*!
*!  Revision 1.2  2007/04/04 03:58:57  elphel
*!  support for new i2c features (hello.c - control i2c timing, fpcf - character device access to i2c)
*!
*!  Revision 1.1.1.1  2007/02/23 10:11:49  elphel
*!  initial import into CVS
*!
*!  Revision 1.12  2006/04/06 07:46:33  elphel
*!  control for canon lenses
*!
*!  Revision 1.11  2006/02/18 18:55:28  elphel
*!  addet FPGA 6 i/o pins capture mode
*!
*!  Revision 1.10  2006/01/11 17:10:05  elphel
*!  *** empty log message ***
*!
*!  Revision 1.9  2006/01/05 05:07:46  spectr_rain
*!  load precalculated gamma table
*!
*!  Revision 1.8  2005/11/23 05:07:42  spectr_rain
*!  up limit for sensor clock
*!
*!  Revision 1.7  2005/08/28 15:46:55  elphel
*!  bug fix in "fpcf -?"
*!
*!  Revision 1.6  2005/08/27 00:46:08  elphel
*!  continue on histograms
*!
*!  Revision 1.5  2005/08/26 02:59:06  elphel
*!  working on histogram
*!
*!  Revision 1.4  2005/07/11 01:33:05  elphel
*!  improved DDR SDRAM phase adjustment
*!
*!  Revision 1.3  2005/05/15 17:39:07  elphel
*!  made DDR SDRAM clock phase adjustment - same as in Theora for model 333 branch
*!
*!  Revision 1.2  2005/05/10 21:08:46  elphel
*!  *** empty log message ***
*!
*!  Revision 1.2  2004/06/18 21:34:13  elphel
*!  added "JPEG_CMD_JUST_STOP" command to stop continuous acquisition mode (actually just a line in help)
*!
*/

/****************** INCLUDE FILES SECTION ***********************************/
#include <stdio.h>

#include <sys/socket.h>
#include <netinet/in.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>

#include <sys/ioctl.h>
#include <fcntl.h>
#include <stdio.h>
#include <stdlib.h>
#include <ctype.h>
#include <errno.h>
#include <unistd.h>
#include <string.h>
//#include <math.h>

//#include <asm/elphel/fpgaconfa.h>
#include <asm/elphel/c313a.h>
#include <asm/elphel/autoexp.h>

#include <asm/elphel/fpgaclocks.h>
#include <asm/elphel/fpgactrl.h>

//#define X313_WA_SD_MANCMD 0x23 // from x3x3.h
#define X313_WA_SD_MODE   0x27 // from x3x3.h
#define X313__RA__STATUS  0x10 // read status register
#define X313_WA_DCM          8  // SDRAM clock phase shift


  #define X313_SR__DCM_OVFL   22
  #define X313_SR__DCM_LOCKED 21
  #define X313_SR__DCM_RDY    20
  #define X313_SR__DCM_EARLY  19
  #define X313_SR__DCM_LATE   18


#define IS_DCM_OVFL(x)   ( x & (1 << X313_SR__DCM_OVFL ))
//#define IS_DCM_LOCK(x) ( x & (1 << X313_SR__DCM_LOCKED ))
#define IS_DCM_LOCK(x)   ( x & (1 << X313_SR__DCM_LOCKED ))
#define IS_DCM_RDY(x)    ( x & (1 << X313_SR__DCM_RDY ))
#define DCM_ERR(x)       (( x >> X313_SR__DCM_LATE ) & 3)
#define IS_DCM_GOOD(x)   (IS_DCM_LOCK(x) && IS_DCM_RDY(x) && !(IS_DCM_OVFL(x)))


/*


#define CY22393_PLLMIN 100.0
#define CY22393_PLLMAX 400.0
#define CY22393_XTAL 20.0
#define CY22393_OUTMAX 166.0
#define CY22393_PMIN 16
#define CY22393_PMAX 1600


static int pll_corr[]= {232,627,835,1044};

*/


#define CLOCK_LOW       20
#define CLOCK_HIGH      127
#define CY22393_SA 0xd2

// saving parameter string in /var/log/fpcf.log if defined
//#define DEBUG_USAGE 1

static char * usage = "Usage: fpcf \n" \
            "-lens D                - write byte D to lens (print to stdout byte read)\n" \
            "-capture T [mask]      - capture I/O pins for T usec (actually will be longer), return number of captured states, then data\n" \
            "                         if mask is specified - AND results with mask, output 2 hex digits if mask> 16, else - 1 digit.\n" \
            "-histogram             - dump histogram\n" \
            "-phase min max [corr]  - adjust optimal readout phase in the range [min,max], min can be negative. Will turn off refresh\n" \
            "                         Apply optional correction [corr] (signed decimal) to the calcualted result.\n" \
            "-dbg B [L [S]]         - read out debug data: B - bit position (decimal), L - register length, S - optional preceeding string\n" \
            "-mem                   - analyze all memory, expecting pattern of 4 16-bit words (will compare to the previous)\n" \
            "-mem N                 - analyze specified number of words (hex) - up to 1000000 expecting pattern of 4 16-bit words\n" \
            "                         N will be rounded to the nearest multiple of 4096\n" \
            "-mem N ptrn0 ptrn1 ptrn2 ptrn3    - write repetitive pattern of 4 16-bit words (hex), read and compare\n" \
            "-raw L   filename      - read hex byte data from filename and put it into frame buffer\n" \
            "                         L (decimal) - full length of the line, including margins. 132 for a single 128x64 supertile \n" \
            "-mcu     filename      - (not used in 333-theora) read hex data and write it to the first MCU(s)\n" \
            "-table A filename      - write quantization/huffman table(s) from file starting att address A(hex word)\n" \
            "-dma 0                 - stop DMA\n" \
            "-dma 1                 - start DMA (descriptors should be filled)\n" \
            "-dma 2                 - start DMA (raw mode). Descriptor array will be built according to current\n" \
            "                         acquisition parameters (image size, word size)\n" \
            "-jpeg 0                - 'reset' JPEG acquire/read pointers\n" \
//            "-jpeg 1                - 'arm' JPEG (compress data with the next frame acquisition)\n"
            "-jpeg 2                - 'get' acquire JPEG data from current frame in memory\n" \
            "-jpeg 3                - 'forget' advance JPEG read pointer to the next frame\n" \
            "-jpeg 5                - acquire and compress one frame\n" \
            "-jpeg 6                - save read pointer\n" \
            "-jpeg 7                - restore read pointer\n" \
            "-jpeg a                - start constant compression to buffer\n" \
            "-jpeg b                - stop constant compression to buffer or acquire just one buffer if it wasn't running\n" \
            "-jpeg c                - rebuild the frames chain backwards from the last acquired. Return number of frames\n" \
            "-jpeg d                - stop constant compression to buffer, don't try to acquire! \n" \
            "-jpeg f                - print some debug data on the serial console\n" \
            "-jctl data             - write JPEG control word (+0x10000 - no header)\n" \

            "-jn data               - get specified number of frames (will add to already asked for if any)\n" \
            "-jl data               - get specified length in 32-bit long words (will stop after frame if got more)\n" \

            "-dr (-drb, -drw, -drl) - get current DMA received data length\n" \
            "-dr A (-drb A) -         read DMA recieved data (bytes) at location A\n" \
            "-dr A N (-drb A N) -     read DMA recieved data (bytes) at locations A through A+N-1\n" \
            "-drw A -                 read DMA recieved data (words) at location A\n" \
            "-drw A N -               read DMA recieved data (words) at locations A through A+N-1\n" \
            "-drl A -                 read DMA recieved data (long words) at location A\n" \
            "-drl A N -               read DMA recieved data (long words) at locations A through A+N-1\n" \
            "-sr A -                  read SDRAM location A\n" \
            "-sr A N -                read SDRAM locations A through A+N-1\n" \
            "-sw{,8,16,32} A D -      write SDRAM location A with data D\n" \
            "-sw{,8,16,32} A D N -    write SDRAM locations A through A+N-1 with data D\n" \
            "-sw{,8,16,32} A D N INC -write SDRAM locations A through A+N-1 with data D, D+INC, ... D+INC*(N-1)\n" \
            "-p FILENAME -            load FPGA with specified bitstream file\n" \
            "-button -                returns 1 if button is pressed, 0 - otherwise\n" \
            "-a -                     read port A input pins\n" \
            "-t TMS LEN D-            send/get JTAG data - TMS=0..1, LEN=0..7 (0==8), D - hex byte\n" \
            "-a D -                   write port A input data\n" \
            "-X N -                   read current cloclk frequency in MHz (shadow)\n" \
            "-X N F -                 program clock output 0,1,2,3 to frequency in MHz (N=3 - only 20MHz), decimal (invisible to driver) - floating pont value\n" \
            "-x N F -                 program clock output 0,1   to frequency in MHz (will be visible to driver)\n" \
            "-s -                     read fpga/clocks state\n" \
            "-r   REGISTER     -      read fpga register (0..ff) using CSP0 (fast access)\n" \
            "-r4  REGISTER     -      read fpga register (0..ff) using CSP4 (slow access)\n" \


            "-rl  REGISTER     -      read fpga register (0..ff) low word using CSP0 (fast access)\n" \
            "-rl4 REGISTER     -      read fpga register (0..ff) low word using CSP4 (slow access)\n" \
            "-rh  REGISTER     -      read fpga register (0..ff) high word using CSP0 (fast access)\n" \
            "-rh4 REGISTER     -      read fpga register (0..ff) high word using CSP4 (slow access)\n" \
            "-w   REGISTER DATA -     write fpga 32-bit register (0..ff) using CSP0 (fast access)\n" \
            "-w4  REGISTER DATA -     write fpga 32-bit register (0..ff) using CSP0 (slow access)\n" \
            "-rw [1..4]         -     read R_WAITSTATES\n" \
            "-ww [1..4] D       -     write R_WAITSTATES\n" \
            "-i2cr8 A           -     read i2c bus 0 at location A (slave address is made of A), 8-bit registers\n" \
            "-i2cr8 A N         -     read i2c bus 0 at location A through A+N-1\n" \
            "-i2cw8 A D         -     write i2c bus 0 at location A with 8-bit data D\n" \
            "-i2cr16 A          -     read i2c bus 0 at location A (slave address is made of A), 16-bit registers\n" \
            "-i2cr16 A N        -     read i2c bus 0 at location A through A+N-1\n" \
            "-i2cw16 A D        -     write i2c bus 0 at location A with 16-bit data D\n" \
            "-sr A N -                read SDRAM locations A through A+N-1\n" \
            "-sw{,8,16,32} A D -      write SDRAM location A with data D\n" \
            "-ir SA RA - read i2c register RA from slave SA (hex)\n"\
            "-iw SA RA DATA - write i2c register, slave address SA, register RA data DATA (hex)\n"\
            "-ir - read all relevant i2c registers from slave 0xd2(0x61)\n"\
            "-c -                     read FPGA command register shadow\n"\
            "-c bit(0..1f of CR) op(0 -nop, 1 - clr, 2 - set, 3 - toggle)\n"\
            "-gamma filename        - write precalculated gamma table\n"\
            "-sysmem N [SEED [SIZE]]- allocate N (decimal) of SIZE (hex, default=20000 (128KB)) chunks, fill them with incrementing data starting with SEED (hex), read back\n" ;
static char * short_usage = "Use fpcf -help for options\n";

/*
int setCYField (int devfd, int addr, int mask, int value) {
    unsigned long d, ra;
    ra= addr & 0xff;
    d=ioctl(devfd, _IO(FPGACONF_IOCTYPE,I2C_READREG), I2C_READARG (0, CY22393_SA, ra)) ;
    if (d & 0xffffff00) return -1;  //bad data
    d^=(d ^ (unsigned long) value) & (unsigned long) mask;
    d=ioctl(devfd, _IO(FPGACONF_IOCTYPE, I2C_WRITEREG ),I2C_WRITEARG(0, CY22393_SA, ra, d));
    if (d & 0xffffff00) return -1;  //bad data
    return 0;  

}
*/
int readSDRAMdummy(void) { // reads SDRAM and ignores result
  int memfd;
  int dummy;
  int res;
  if ((memfd = open("/dev/fsdram", O_RDONLY))<0)  {printf("error opening /dev/fsdram\r\n"); return -1;}
  res=read(memfd,&dummy,4);
  close (memfd);
  if (res<4) {printf("readSDRAMdummy failed\n"); return -1; }
  return 0;
}

//        res=(res<<1) || ( (ioctl(devfd, _IO(FPGACONF_READREG4, 0x70 ), 0) & 2)>>1);
//        ioctl(devfd, _IO(FPGACONF_WRITEREG, 0x70 ), 0x23 | ((n & 0x80)?0x10:0)); // 
  void usleepFPGA(int devfd, int dly) { // <0.5 sec, devfd should be opened
    int t0,t1,t;
    ioctl(devfd, _IO(FPGACONF_WRITEREG, 0x47 )); // latch timer
    t0=ioctl(devfd, _IO(FPGACONF_READREG, 0x44 ), 0);
    t1=t0+dly;
    if (t1>=1000000) t1-=1000000;
    t=t0;
    if (t1>t0) {
      while (t<t1) {
        ioctl(devfd, _IO(FPGACONF_WRITEREG, 0x47 )); // latch timer
        t=ioctl(devfd, _IO(FPGACONF_READREG, 0x44 ), 0);
      }
    } else {
      while ((t>t0) || (t<t1)) {
        ioctl(devfd, _IO(FPGACONF_WRITEREG, 0x47 )); // latch timer
        t=ioctl(devfd, _IO(FPGACONF_READREG, 0x44 ), 0);
      }
    }
  }  

#define FPCF_SDBUFFER_SIZE 0x800
int main (int argc, char *argv[]) {
  const unsigned char syncseq[]={0xff,0xff,0xff,0xff,0xaa,0x99,0x55,0x66};

  unsigned char charheadbuf[8];
  unsigned short usbuf[FPCF_SDBUFFER_SIZE];
  unsigned char  * usbuf8 =  (unsigned char *)  usbuf;
  unsigned short * usbuf16 = (unsigned short *) usbuf;
  unsigned long  * usbuf32 = (unsigned long *)  usbuf;
    int retry,corr;
    char * cp;
    int i,a;
    int j=0;
    int n,res;
    double f;
    int devfd;
//    double dif, bdif,k;
//    int divmn,divmx,divi,p,q,pllc;
    int bp=0;
    int bq=0;
//    int bdiv=0;
    unsigned long d, sa, ra, rd,fs, ll, nl, nt;
    int ifd;
    int retr;
    unsigned char b,b0;
//    unsigned short usd,usi;
    unsigned long uld,uli;
  int shft;
  int testcs=0;
  int testnum=0;
    int iorw_args=0;
    int ws;
  int tables[4096];
  unsigned int ptrn[2];
  unsigned int ands[2];
  unsigned int ors[2];
  unsigned short * ands16 = (unsigned short *) ands;
  unsigned short * ors16 =  (unsigned short *) ors;
  unsigned short * ptrn16 = (unsigned short *) ptrn;
  int nerr;
  int comp_mode;
  int seed;
  int ** memchunks= (int **) tables;

  unsigned char * btables= (unsigned char *) tables;
    const int bits_in_byte[]={0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,\
                              1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5,\
                              1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5,\
                              2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6,\
                              1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5,\
                              2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6,\
                              2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6,\
                              3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7,\
                              1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5,\
                              2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6,\
                              2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6,\
                              3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7,\
                              2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6,\
                              3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7,\
                              3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7,\
                              4,5,5,6,5,6,6,7,5,6,6,7,6,7,7,8};                              

 char fline[1024];
  FILE *  tfile;
  char *  ep;
  char    fvx[5]="%08x\0";
  int     mn,mx;
  int     dqmn=0;
  int     dqmx=0;
  int     state;
        int gamma_fd;
        int autoexp_fd;
   int capByteOut;
   int capByteIn;
   int capBitCntr;
   int capByteCntr;
   int capLastByte;
   int capByte;
   int capFormat=0;

#ifdef DEBUG_USAGE
  FILE *  fpcflog;
  if ((fpcflog = fopen("/var/log/fpcf.log", "w"))==NULL) {printf("error opening file %s\n","/var/log/fpcf.log"); return -1;}
  
  for (i=0; i<argc;i++) fprintf (fpcflog, " %s", argv[i]);
  fclose(fpcflog);
#endif
   if (argc<2) {printf(short_usage); return 0;}
   if ((strcasecmp(argv[1], "-help")==0) || (strcasecmp(argv[1], "-?")==0)) {
     printf(usage);
     return 0;
   }

   if(strcasecmp(argv[1], "-lens") == 0) {
      if(argc <3) { // read capture
         printf("need data to send to the lens\n");
         return -1;
      }
      
      if ((devfd = open("/dev/fpgaio", O_RDWR))<0)  {printf("error opening /dev/fpgaio\r\n"); return -1;}
      for (j=2; j< argc; j++) {
        res= ioctl(devfd, _IO(FPGACONF_CANON_IOBYTE, 0 ),(unsigned long) strtoll (argv[j],&cp,16));
        tables[j-2]=res;
      }  
      close (devfd);
      for (j=2; j< argc; j++) {
        printf ("%2x ",tables[j-2]);
      }
      printf("\n");  
      return 0;
   }
   
   
   if(strcasecmp(argv[1], "-capture") == 0) {
      j=0xff;
      if (argc >3) j=strtol (argv[3],&cp,10);
      j &= 0xff;
      if(argc <3) { // read capture
         printf("need capture duration (usec)\n");
         return -1;

      }
      if ((devfd = open("/dev/fpgaio", O_RDWR))<0)  {printf("error opening /dev/fpgaio\r\n"); return -1;}
      n= ioctl(devfd, _IO(FPGACONF_START_CAPTURE, j ), strtol (argv[2],&cp,10));
      printf ("%d\n",n);
      for (i=0;i<n;i++) {
        if (j<16) printf ("%1x",j & ioctl(devfd, _IO(FPGACONF_READ_CAPTURE, 0 ), 0));
        else      printf ("%2x",j & ioctl(devfd, _IO(FPGACONF_READ_CAPTURE, 0 ), 0));
      }
      printf ("\n");
      close (devfd);
      return 0;
   }
   if(strcasecmp(argv[1], "-capbytes") == 0) {
      if (argc >4) capFormat=strtol (argv[4],&cp,10);
      j=0xff;
      if (argc >3) j=strtol (argv[3],&cp,10);
      j &= 0xff;
      if(argc <3) { // read capture
         printf("need capture duration (usec)\n");
         return -1;

      }
      if ((devfd = open("/dev/fpgaio", O_RDWR))<0)  {printf("error opening /dev/fpgaio\r\n"); return -1;}
      n= ioctl(devfd, _IO(FPGACONF_START_CAPTURE, j ), strtol (argv[2],&cp,10));
      printf ("%d\n",n);
      capByteOut=0;
      capByteIn=0;
      capBitCntr=0;
      capByteCntr=0;
      capLastByte=7;
      for (i=0;i<n;i++) {
        capByte=ioctl(devfd, _IO(FPGACONF_READ_CAPTURE, 0 ), 0);
        if (!(capLastByte & 1) && (capByte & 1)) {
          capByteOut= (capByteOut << 1) | ((capByte & 4)? 1:0);
          capByteIn=  (capByteIn  << 1) | ((capByte & 2)? 1:0);
          capBitCntr++;
          if (capBitCntr==8) {
            if      (capFormat==0) printf (" %2x(%2x)",capByteOut,capByteIn);
            else if (capFormat==1)  printf ("%2x  %2x",capByteOut,capByteIn);
            else if (capFormat==2)  printf ("%2x  %2x\n",capByteOut,capByteIn);
            capByteOut=0;
            capByteIn=0;
          } else if (capBitCntr>8) {
            if      (capFormat==0) printf (" [%1x/%1x]",capByteOut,capByteIn);
            else if (capFormat==1)  printf ("  [%1x/%1x]\n",capByteOut,capByteIn);
            capByteOut=0;
            capByteIn=0;
            capBitCntr=0;
            capByteCntr++;
          }
        }
        capLastByte=capByte;
      }
      printf ("\n");
      printf ("Exchanged %d bytes, %d bits left\n", capByteCntr,capBitCntr);
      if (capBitCntr>0)  printf ("Left: %2x(%2x)\n",capByteOut,capByteIn);
      close (devfd);
      return 0;
   }
        if(strcasecmp(argv[1], "-gamma") == 0) {
                if(argv[2] == NULL) {
                        printf("need gamma table filename\n");
                        return -1;
                }
                if((autoexp_fd = open(AUTOEXP_DEV_NAME, O_RDWR)) < 0) {
                        printf("failed to open %s\n", AUTOEXP_DEV_NAME);
                        return -1;
                }
                if((gamma_fd = open(argv[2], O_RDONLY)) < 0) {
                        printf("failed to open %s\n", AUTOEXP_DEV_NAME);
                        return -1;
                }
                ioctl(autoexp_fd, _IO(IOC_AUTOEXP_GAMMA_TABLE, 0));
                while((i = read(gamma_fd, (void *)usbuf, FPCF_SDBUFFER_SIZE)) > 0)
                        if(write(autoexp_fd, (void *)usbuf, i) < 0) {
                                printf("error write gamma\r\n");
                                break;
                        }
                close(gamma_fd);
                close(autoexp_fd);
                return 0;
        }
   if (strcasecmp(argv[1], "-histogram")==0) {
         if ((devfd = open("/dev/fpgaio", O_RDWR))<0)  {printf("error opening /dev/fpgaio\r\n"); return -1;}
         ioctl(devfd, _IO(FPGACONF_WRITEREG, 0x42 ), 0);
         for (i=0; i<4;i++) {
           res=0;
           for (j=0; j<256; j++) {
             n=ioctl(devfd, _IO(FPGACONF_READREG4, 0x43 ), 0);
             res+=n;
             printf ("%6x",n);
             if ((j & 0xf)==0xf) printf("\n");
             if ((j & 0xff)==0xff) printf("\n");
           }
           printf ("total=0x%x (%d)\n",res,res);
         }
         close (devfd);
         return 0;
   }
#if 0
#define X313_SR__DCM_OVFL    28
#define X313_SR__DCM_LOCKED  25
//#define X313_SR__DCM_STOPPED 24
#define X313_SR__DCM_RDY    23
#define X313_SR__DCM_EARLY  22
#define X313_SR__DCM_LATE   21

#define IS_DCM_OVFL(x)   ( x & (1 << X313_SR__DCM_OVFL ))
//#define IS_DCM_LOCK(x) ( x & (1 << X313_SR__DCM_LOCKED ))
#define IS_DCM_LOCK(x)   ( x & (1 << X313_SR__DCM_LOCKED ))
#define IS_DCM_RDY(x)    ( x & (1 << X313_SR__DCM_RDY ))
#define DCM_ERR(x)       (( x >> X313_SR__DCM_LATE ) & 3)
#define IS_DCM_GOOD(x)   (IS_DCM_LOCK(x) && IS_DCM_RDY(x) && !(IS_DCM_OVFL(x)))
#endif
#define DCM_RETRY 100
#define phase_noise_margin 5
   if (strcasecmp(argv[1], "-phase")==0) { // adjust phase
      if (argc<4) {printf("min and max phase shift(decimal) required\r\n");return -1;}
      mn= strtol (argv[2],&cp,10);
      mx= strtol (argv[3],&cp,10);
      corr=0;
      if (argc>4) corr= strtol (argv[4],&cp,10);
      if ((devfd = open("/dev/fpgaio", O_RDWR))<0)  {printf("error opening /dev/fpgaio\r\n"); return -1;}
//reset phase
      ioctl(devfd, _IO(FPGACONF_WRITEREG, X313_WA_DCM ), 3); // reset phase
      for (retry=DCM_RETRY;retry>0;retry--) {
           a=ioctl(devfd, _IO(FPGACONF_READREG, X313__RA__STATUS ), 0);
           if (IS_DCM_LOCK(a)) break;
      }
      if (retry <=0) {
        printf ("DCM does not lock after bein reset (status=%x)\n",a);
        close (devfd);
        return -1;
      }
// go to lower limit
      if (mn <0) {
        for (i=0; i>mn;i--) {
          for (retry=DCM_RETRY;retry>0;retry--) {
             a=ioctl(devfd, _IO(FPGACONF_READREG, X313__RA__STATUS ), 0);
             if (IS_DCM_GOOD (a)) break;
          }
          if (retry <=0) {
            printf ("DCM phase probably reached lower limit (status=%x). Try >%d (instead of %d)\n",a,i,mn);
            ioctl(devfd, _IO(FPGACONF_WRITEREG, X313_WA_DCM ), 3); // reset phase
            close (devfd);
            return -2;
          }
          ioctl(devfd, _IO(FPGACONF_WRITEREG, X313_WA_DCM ), 1); // increase phase
        }
      } else if (mn>0) {
        for (i=0; i<mn;i++) {
          for (retry=DCM_RETRY;retry>0;retry--) {
             a=ioctl(devfd, _IO(FPGACONF_READREG, X313__RA__STATUS ), 0);
             if (IS_DCM_GOOD (a)) break;
          }
          if (retry <=0) {
            printf ("DCM phase lower limit is probably too high (status=%x). Try <%d (instead of %d)\n",a,i,mn);
            ioctl(devfd, _IO(FPGACONF_WRITEREG, X313_WA_DCM ), 3); // reset phase
            close (devfd);
            return -3;
          }
          ioctl(devfd, _IO(FPGACONF_WRITEREG, X313_WA_DCM ), 2); // decrease phase
        }
      }
#if 0 // What the hell was that???
// reset and reprogram SDRAM (twice, to be sure phase was settled)
//      ra=X313_WA_SD_MANCMD; // NOTE: WAS BUG - 0x20, needed 0x23
      ra=0x20;  // NOTE: WAS BUG - 0x20, needed 0x23
      rd=0x15555; // all channels reset, stop refresh (so SDRAM will be initialized when opened)
      for (i=0;i<2;i++) {
        ioctl(devfd, _IO(FPGACONF_WRITEREG, ra ), rd);
        if (readSDRAMdummy()<0) {close (devfd); return -1;}
      }
#endif
// scan all phases in [min,max] storing data in tables[];
      for (i=0; i < ((mx-mn)+1); i++) {
        if (i>0) { // decrease phase by 1 - all but first;
          for (retry=DCM_RETRY;retry>0;retry--) {
             a=ioctl(devfd, _IO(FPGACONF_READREG, X313__RA__STATUS ), 0);
             if (IS_DCM_GOOD (a)) break;
          }
          if (retry <=0) {
            i+=mn;
            if (i<0) {
              printf ("DCM phase probably reached lower limit (pass2, status=%x). Try >%d (instead of %d)\n",a,i,mn);
              ioctl(devfd, _IO(FPGACONF_WRITEREG, X313_WA_DCM ), 3); // reset phase
              close (devfd);
              return -3;
            } else {
              printf ("DCM phase high limit is probably too high (status=%x). Try <%d (instead of %d)\n",a,i,mx);
              ioctl(devfd, _IO(FPGACONF_WRITEREG, X313_WA_DCM ), 3); // reset phase
              close (devfd);
              return -4;
            }
          }
          ioctl(devfd, _IO(FPGACONF_WRITEREG, X313_WA_DCM ), 2); // decrease phase
        }
// NEW: reset PLL in SDRAM after each phase change - is that really needed?
        ioctl(devfd, _IO(FPGACONF_WRITEREG, X313_WA_SD_MODE ), 0); // SDRAM, refresh - off - will reinit on attempt to read
// read, reset errors and read again, so phase will be settled after change
        if (readSDRAMdummy()<0) {close (devfd); return -1;}
        ioctl(devfd, _IO(FPGACONF_WRITEREG, X313_WA_DCM ), 0);
        if (readSDRAMdummy()<0) {close (devfd); return -1;}
//        tables[i]=(ioctl(devfd, _IO(FPGACONF_READREG, X313__RA__STATUS ), 0)>>21) & 3;
        tables[i]=DCM_ERR(ioctl(devfd, _IO(FPGACONF_READREG, X313__RA__STATUS ), 0));
      }
// calculate and report results
      for (i=0; i<((mx-mn)+1); i++) {
        printf (" %d",tables[i]);
        if ((i & 0xf)==0xf) printf ("\r\n");
      }
      printf ("\r\n");

      state=0; // 0 - looking for "1", 1 - looking for "3", 2 - looking for 2, 3 - done
      for (i=0;(i<=(mx-mn)) && (state<3); i++) 
        switch (state) {
        case 0: if      (tables[i]==1)  state = 1; break;
        case 1: if      (tables[i]==3) {state = 2; dqmn=mn+i;dqmx=dqmn;}
                else if (tables[i]==2)  state = 0;
                break;
        case 2: if      (tables[i]==2)  state = 3;
                else if (tables[i]==1)  state = 1;
                else     dqmx=mn+i;
                break;
        }
      if (state < 2) {close (devfd);printf("failed to find lower margin\n"); return -2;}
      if (state < 3) {close (devfd);printf("failed to find upper margin\n"); return -2;}
      printf ("phase uncertainty range = %d (minimal %d, maximal - %d)\r\n",dqmx-dqmn,dqmn,dqmx);
      printf ("optimal phase = %d\r\n",(dqmx+dqmn)>>1);
      if (corr) {
         printf ("manually corrected optimal phase = %d\r\n",((dqmx+dqmn)>>1)+corr);
      }
      corr+=((dqmx+dqmn)>>1);
//set the calculated phase (it was now left at mx      
      if (corr <= mx) {
        for (i=mx; i > corr; i--) {
          for (retry=DCM_RETRY;retry>0;retry--) {
             a=ioctl(devfd, _IO(FPGACONF_READREG, X313__RA__STATUS ), 0);
             if (IS_DCM_GOOD (a)) break;
          }
          if (retry <=0) {
            if (i>(mx-5)) {
              printf ("DCM phase high limit is probably too high (pass3, status=%x). Try <%d (instead of %d)\n",a,i,mx);
              ioctl(devfd, _IO(FPGACONF_WRITEREG, X313_WA_DCM ), 3); // reset phase
              close (devfd);
              return -4;
            } else {
              printf ("DCM failed to set to the optimal phase ( should not be so - status=%x at phase %d)\n",a,i);
              ioctl(devfd, _IO(FPGACONF_WRITEREG, X313_WA_DCM ), 3); // reset phase
              close (devfd);
              return -5;
            }
          }
          ioctl(devfd, _IO(FPGACONF_WRITEREG, X313_WA_DCM ), 1); // increase phase
        }
      } else {
        for (i=mx; i < corr; i++) {
          for (retry=DCM_RETRY;retry>0;retry--) {
             a=ioctl(devfd, _IO(FPGACONF_READREG, X313__RA__STATUS ), 0);
             if (IS_DCM_GOOD (a)) break;
          }
          if (retry <=0) {
            printf ("DCM corrected phase (%d) is probably too high. Failed at %d (with status=%x)\n",corr,i,a);
            ioctl(devfd, _IO(FPGACONF_WRITEREG, X313_WA_DCM ), 3); // reset phase
            close (devfd);
            return -4;
          }
          ioctl(devfd, _IO(FPGACONF_WRITEREG, X313_WA_DCM ), 2); // decrease phase
        }
      }
// now turn off refresh so SDRAM will be initialized next time
#if 0 // What the hell was that???
      ra=0x20;
      rd=0x15555; // all channels reset, stop refresh (so SDRAM will be initialized when opened)
      ioctl(devfd, _IO(FPGACONF_WRITEREG, ra ), rd);      
#endif

      ioctl(devfd, _IO(FPGACONF_WRITEREG, X313_WA_SD_MODE ), 0); // SDRAM, refresh - off - will reinit on attempt to read
      readSDRAMdummy();
                // need to automatic check result
      printf("result=OK\n");

      close (devfd);
      return 0;
   }
   if (strcasecmp(argv[1], "-dbg")==0) { // read out internal debug data
     if (argc<3) {printf("Bit position and bit width are expected (optionally followed by preceeding text ('_' instead of spaces))\r\n");return -1;}
     bp= strtol (argv[2],&cp,10);
     if (argc >3) bq= strtol (argv[3],&cp,10);
     else bq=32;
     if (bq>32) bq=32;
     if ((devfd = open("/dev/fpgaio", O_RDWR))<0)  {printf("error opening /dev/fpgaio\r\n"); return -1;}
     res=ioctl(devfd, _IO(FPGACONF_WRITEREG, 0x10 ),0); // strobe all data
     for (i=0; i<bp;i++) res=ioctl(devfd, _IO(FPGACONF_READREG4, 0x10 ),0);
     d=0;
     for (i=0;i<32;i++)
       if ((i<bq) && (ioctl(devfd, _IO(FPGACONF_READREG4, 0x10 ),0) & 0x40000000))  d=(d>>1) | 0x80000000;
       else d=(d>>1) & 0x7fffffff;
     close (devfd);
     if (argc >4) {
      for (cp=argv[4];cp[0];cp++) if (cp[0]!='_') printf("%c",cp[0]);
                                  else printf(" ");
      printf(" ");
     }
     fvx[2]='1'+(bq>>2);
     printf(fvx,d);
     printf("\n");
     return 0;
   }

   if (strcasecmp(argv[1], "-tr")==0) { // test register A N
     if (argc<4) {printf("A nad N (hex) are expected\r\n");return -1;}
     a= strtol (argv[2],&cp,16);
     n= strtol (argv[3],&cp,16);
     ands[0]=0xffffffff;
     ors[0]=0;
     if ((devfd = open("/dev/fpgaio", O_RDWR))<0)  {printf("error opening /dev/fpgaio\r\n"); return -1;}
     for (i=0; i<n;i++) {
       j=ioctl(devfd, _IO(FPGACONF_READREG, a ),0);
       ands[0] &= j;
       ors[0] |= j;
     }
     printf ("and=0x%x, or=0x%x\n",ands[0],ors[0]);
     close(devfd);
     return 0;
   }
    
   if (strcasecmp(argv[1], "-mem")==0) { // line width (in pixels) and file name - starts at address 0
      comp_mode=0; // compare with previous
      n=0x2000000; // full memory size in 16-bit words
      if (argc>=3) {
        n= strtol (argv[2],&cp,16);
        if (argc >=7) {
          comp_mode=1; // compare with pattern
          ptrn16[0]= strtol (argv[3],&cp,16);
          ptrn16[1]= strtol (argv[4],&cp,16);
          ptrn16[2]= strtol (argv[5],&cp,16);
          ptrn16[3]= strtol (argv[6],&cp,16);
        }
      }
      if (n>0x2000000) n=0x2000000;
      n=n>>12; // 4096 (of short int) pages
      if (n<1) n=1;
// fill memory with pattern if needed
      if (comp_mode) {
        for (i=0;i<2048;i+=2) {tables[i]=ptrn[0];tables[i+1]=ptrn[1];}
        if ((devfd = open("/dev/fsdram", O_RDWR))<0)  {printf("error opening /dev/fsdram\r\n"); return -1;}
        for (i=0;i<n;i++) if ((res=write(devfd,tables,8192))<8192) {
            printf("write failed, returned %d, expected - %d\n",res, 8192);
            close (devfd);
            return -1;
        }
        close (devfd);
      }  
// now read and analyze      
      if ((devfd = open("/dev/fsdram", O_RDONLY))<0)  {printf("error opening /dev/fsdram\r\n"); return -1;}
      ands[0]=0xffffffff;
      ands[1]=0xffffffff;
      ors[0]=0;
      ors[1]=0;
      nerr=0;
      for (i=0;i<n;i++) {
        if ((res=read(devfd,tables,8192))<8192) {
          printf("read failed, returned %d, expected - %d\n",res, 8192);
          close (devfd);
          return -1;
        }
        for (j=0;j<2048;j+=2) {
          ands[0] &= tables[j];
          ands[1] &= tables[j+1];
          ors[0]  |= tables[j];
          ors[1]  |= tables[j+1];
        }
        if (comp_mode) {
          for (j=0;j<2048;j+=2) {
            tables[j]   ^= ptrn[0];
            tables[j+1] ^= ptrn[1];
          }
        } else {
          for (j=2;j<2048;j+=2) {
            tables[j-2] ^= tables[j];
            tables[j-1] ^= tables[j+1];
          }
          tables[2046]=0;
          tables[2047]=0;
        }
        for (j=0;j<8192;j++)  {
         nerr+=bits_in_byte[btables[j]];
//         if (btables[j]) printf("btables[%d]=0x%x, bits_in_byte[btables[%d]]=%d, nerr=%d\n",j,(int) btables[j],j,bits_in_byte[btables[j]],nerr);
        } 
      }
                // print test result for automatic tests
                if(nerr == 0)
                        printf("result=OK\n");
                else
                        printf("result=FAIL\n");
      printf                ("wrong bits - 0x%x (in 0x%x tested 16-bit words)\n",nerr,(n<<12));
      printf                ("and     %4x %4x %4x %4x\n",ands16[0],ands16[1],ands16[2],ands16[3]);
      printf                ("or      %4x %4x %4x %4x\n",ors16[0], ors16[1], ors16[2], ors16[3]);
      if (comp_mode) printf ("pattern %4x %4x %4x %4x\n",ptrn16[0],ptrn16[1],ptrn16[2],ptrn16[3]);
      

      close (devfd);
      return 0;
   }

   
   
         
   if (strcasecmp(argv[1], "-raw")==0) { // line width (in pixels) and file name - starts at address 0
      if (argc<3) {printf("Line length (decimal, pixels) and filename with pixel data (hex bytes)\r\n");return -1;}
      ll= strtol (argv[2],&cp,10);

      if ((tfile = fopen(argv[3], "r"))==NULL) {printf("error opening file %s\n",argv[3]); return -1;}
      if ((devfd = open("/dev/fsdram", O_RDWR))<0)  {printf("error opening /dev/fsdram\r\n"); fclose (tfile); return -1;}
      d=0;
      n=0;
      nl=0; // line number
      
      fline[1023]=0;
      while (((cp=fgets(fline,1023,tfile)) !=NULL) && (n<2048)) {
       while (((d=strtol (cp,&ep,16)), ((ep-fline)<strlen(fline))) && (n<2048) && (ep != cp)){
         btables[n++]=d;
         cp=ep;
         if (n>=ll) {
           for (i=0; i<ll; i+=256) {
             nt=(nl>>4)*(((ll-1)>>8)+1)+(i>>8); // number of block with the same RA
             sa=((nt >>  1) << 13) + //in channel 3 blocks with the same RA go in pairs - each 512*16 pixels/bytes
                ((nt &   1) << 8)  + // odd blocks add 256 in channel3 pointer
                ((nl & 0xf) << 9);  // "lines" in channel 3 are 512 bytes long
             lseek(devfd,sa,0);
             write(devfd,&btables[i],((ll-i) > 256)?256:(ll-i));
           }
           nl++;
           n=0;
         }
       }
      }
      fclose (tfile);
      close (devfd);
      printf("read %d lines, each %d pixels long\n", (int) nl, (int) ll);
      return 0;
   }
   
   
   
   if (strcasecmp(argv[1], "-mcu")==0) {
      sa=0x280000;   
      if (argc<2) {printf("Address and filename\r\n");return -1;}

      if ((tfile = fopen(argv[2], "r"))==NULL) {printf("error opening file %s\n",argv[2]); return -1;}
      d=0;
      n=0;
      fline[1023]=0;

                
      while (((cp=fgets(fline,1023,tfile)) !=NULL) && (n<2048)) {
       while (((d=strtol (cp,&ep,16)), ((ep-fline)<strlen(fline))) && (n<2048) && (ep != cp)){
         btables[n++]=d;
         cp=ep;
       }
      }
      fclose (tfile);
      printf("read %d elements\n",n);
// image format is expected to be not more than 256 pixels wide, 8 bit
      if ((devfd = open("/dev/fsdram", O_RDWR))<0)  {printf("error opening /dev/fsdram\r\n"); return -1;}
      for (i=0;i<n;i+=16){
        lseek(devfd,sa+ ((i & 0xf0) << 4)+((i & 0xf00)>>4),0);
        write(devfd,&btables[i],16);
      }
      close (devfd);
      return 0;
   }    
        if (argv[1][0] != '-'){printf(usage); return 0;}
   if (strcasecmp(argv[1], "-table")==0) {
      if (argc<3) {
// no reading table for now      
/*      
         if ((devfd = open("/dev/fpgaio", O_RDWR))<0)  {printf("error opening /dev/fpgaio\r\n"); return -1;}
         for (i=0; i<256; i++) {
           ioctl(devfd, _IO(FPGACONF_WRITEREG, 0x0d ), i);
           ioctl(devfd, _IO(FPGACONF_WRITEREG, 0x0d ), i);
           ioctl(devfd, _IO(FPGACONF_WRITEREG, 0x0d ), i);
           printf ("%6x",ioctl(devfd, _IO(FPGACONF_WRITEREG, 0x14 ), 0));
           if ((i & 0x7)==0x7) printf("\n");
           if ((i & 0x3f)==0x3f) printf("\n");
         }
         for (i=512; i<1024; i++) {
           ioctl(devfd, _IO(FPGACONF_WRITEREG, 0x0d ), i);
           ioctl(devfd, _IO(FPGACONF_WRITEREG, 0x0d ), i);
           ioctl(devfd, _IO(FPGACONF_WRITEREG, 0x0d ), i);
           printf ("%6x",ioctl(devfd, _IO(FPGACONF_WRITEREG, 0x14 ), 0));
           if ((i & 0xf)==0xf) printf("\n");
           if ((i & 0xff)==0xff) printf("\n");

         }
         close (devfd);
*/         
         return 0;
      }
      if (argc==3)  {
        sa=0;
        cp=argv[2];
      } else {
        sa= strtol (argv[2],&cp,16);
        cp=argv[3];
      }
//
      // try reading table data to memory
      if ((tfile = fopen(cp, "r"))==NULL) {printf("error opening file %s\n",cp); return -1;}
      d=0;
      i=0;
      fline[1023]=0;
                
      while (((cp=fgets(fline,1023,tfile)) !=NULL) && (i<1024)) {
       while (((d=strtol (cp,&ep,16)), ((ep-fline)<strlen(fline))) && (i<2048) && (ep != cp)){
         tables[i++]=d;
         cp=ep;
       }
      }
      fclose (tfile);
        
      printf("read %d elements\n",i);
/*
      for (j=0;j<i;j++) {
        printf("%6x ",tables[j]);
        if ((j & 0xf)==0xf) printf("\n");

      }
*/
      if ((devfd = open("/dev/fpgaio", O_RDWR))<0)  {printf("error opening /dev/fpgaio\r\n"); return -1;}

//      ioctl(devfd, _IO(FPGACONF_WRITEREG, 0x0d ), sa);
//      for (j=0;j<i;j++) ioctl(devfd, _IO(FPGACONF_WRITEREG, 0x0e ), tables[j]);
      ioctl(devfd, _IO(FPGACONF_WRITEREG, 0x0e ), sa);
      for (j=0;j<i;j++) ioctl(devfd, _IO(FPGACONF_WRITEREG, 0x0f ), tables[j]);
      printf ("%x\n",(int) d);
      close (devfd);
      return 0;
    }

    if (strcasecmp(argv[1], "-jpeg")==0) {
      if (argc<3) {printf("Need JPEG command number\r\n");return -1;}
      i= strtol (argv[2],&cp,16);
// had a problem turning off compression mode from the sctl.cgi as "/dev/ccam_dma.raw" was busy.
// changed (only for "d") to "/dev/sensorpars" that does not check for busy
      if (i==0x0d)
        {
      if ((devfd = open("/dev/sensorpars", O_RDONLY))<=0) {
          printf("error opening /dev/sensorpars, errno=%d\n",errno);
#ifdef DEBUG_USAGE
          fpcflog = fopen("/var/log/fpcf.log", "a");
          fprintf (fpcflog, " error opening /dev/sensorpars, errno=%d\n",errno);
// still getting errno=9 "Bad file numer"???
          fclose(fpcflog);
#endif
          return -1;}
      } else {
        if ((devfd = open("/dev/ccam_dma.raw", O_RDONLY))<=0) {
          printf("error opening /dev/ccam_dma.raw, errno=%d\n",errno);
#ifdef DEBUG_USAGE
          fpcflog = fopen("/var/log/fpcf.log", "a");
          fprintf (fpcflog, " error opening /dev/ccam_dma.raw, errno=%d\n",errno);
          fclose(fpcflog);
#endif
          return -1;}
      }
      res=ioctl(devfd, _IO(CMOSCAM_IOCTYPE, IO_CCAM_JPEG ), i);
      printf("0x%x\n",res);
#ifdef DEBUG_USAGE
//  FILE *  fpcflog;
  if ((fpcflog = fopen("/var/log/fpcf.log", "a"))==NULL) {printf("error opening file %s\n","/var/log/fpcf.log"); return -1;}
  
   fprintf (fpcflog, " 0x%x\n",res);
  fclose(fpcflog);
#endif
      close (devfd);
      return 0;
    }

    if (strcasecmp(argv[1], "-jctl")==0) {
      if (argc<3) {printf("Need JPEG control word\r\n");return -1;}
      i= strtol (argv[2],&cp,16);
      if ((devfd = open("/dev/ccam_dma.raw", O_RDONLY))<=0) {printf("error opening /dev/ccam_dma.raw\n"); return -1;}
      res=ioctl(devfd, _IO(CMOSCAM_IOCTYPE, IO_CCAM_JPEG_CTRL ), i);
      close (devfd);
      return 0;
    }
    if (strcasecmp(argv[1], "-jn")==0) {
      if (argc<3) {printf("Need number of frames to acquire\r\n");return -1;}
      i= strtol (argv[2],&cp,16);
      if ((devfd = open("/dev/ccam_dma.raw", O_RDONLY))<=0) {printf("error opening /dev/ccam_dma.raw\n"); return -1;}
      res=ioctl(devfd, _IO(CMOSCAM_IOCTYPE, IO_CCAM_JPEG_GET_N ), i);
      close (devfd);
      return 0;
    }
    if (strcasecmp(argv[1], "-jl")==0) {
      if (argc<3) {printf("Need dadat length (in 32-bit words) to acquire\r\n");return -1;}
      i= strtol (argv[2],&cp,16);
      if ((devfd = open("/dev/ccam_dma.raw", O_RDONLY))<=0) {printf("error opening /dev/ccam_dma.raw\n"); return -1;}
      res=ioctl(devfd, _IO(CMOSCAM_IOCTYPE, IO_CCAM_JPEG_GET_L ), i);
      close (devfd);
      return 0;
    }
    if (strcasecmp(argv[1], "-dma")==0) {
      if (argc<3) {printf("Need DMA command number\r\n");return -1;}
          i= strtol (argv[2],&cp,16);
      if ((i<0) || (i>2)) {printf("Supported DMA commands are 0,1 and 2 only\r\n");return -1;}
      if ((devfd = open("/dev/ccam_dma.raw", O_RDONLY))<=0) {printf("error opening /dev/ccam_dma.raw\n"); return -1;}
      res=ioctl(devfd, _IO(CMOSCAM_IOCTYPE, IO_CCAM_DMA ), i);
      close (devfd);
      return 0;
    }

    if ((strcasecmp(argv[1], "-dr" )==0) || 
        (strcasecmp(argv[1], "-drb")==0) ||
        (strcasecmp(argv[1], "-drw")==0) ||
        (strcasecmp(argv[1], "-drl")==0)) {
      ws=0;
      if (strcasecmp(argv[1], "-drw")==0) ws=1;
      if (strcasecmp(argv[1], "-drl")==0) ws=2;
      if (argc<3) {
            if ((devfd = open("/dev/ccam_dma.raw", O_RDONLY))<=0) {printf("error opening /dev/ccam_dma.raw\n"); return -1;}
        fs=lseek(devfd,0,2);
        if (fs>=0) fs>>=ws;
        printf("DMA received 0x%x (%d) ", (int) fs, (int) fs);
        if      (ws==0) printf("bytes\n");
        else if (ws==1) printf("words\n");
        else            printf("long words\n");
        close (devfd);
        return 0;
      }
          sa= strtol (argv[2],&cp,16);
      n=1; if (argc >3) n= strtol (argv[3],&cp,16);
      if ((devfd = open("/dev/ccam_dma.raw", O_RDONLY))<=0) {printf("error opening /dev/ccam_dma.raw\n"); return -1;}
      while (n>0) {
        i=n; if (i>((FPCF_SDBUFFER_SIZE<<1)>>ws)) i=((FPCF_SDBUFFER_SIZE<<1)>>ws);
        if ((res=lseek(devfd,sa<<ws,0))<0) {
          printf("lseek failed, returned %d\n",res);
          close (devfd);
          return -1;
        }
//    printf("lseek OK, returned %d\n",res);
        if ((res=read(devfd,usbuf,i<<ws))<(i<<ws)) {
          if (res!=0) printf("\nread failed, returned %d bytes, expected - %d\n",res, (i<<ws));
          if (res <= 0 ) {
            close (devfd);
            return -1;
          }
          i=(res>>ws);
        }
// print buffer
        for (j=0;j<i;j++) {
          if ( ((sa+j) & 0x0f) == 0) printf("\n%06x:",(int) (sa+j));
          if      (ws==0) printf (" %2x", (int) usbuf8 [j]);
          else if (ws==1) printf (" %4x", (int) usbuf16[j]);
          else            printf (" %8x", (int) usbuf32[j]);
        }
        sa += i;
        n  -= i;
      }
      printf("\n");
      close (devfd);
      return 0;


    }

    shft=-1;
    res=0;
    if (strcasecmp(argv[1], "-sr")   ==0) shft=1;
    if (strcasecmp(argv[1], "-sr8")  ==0) shft=0;
    if (strcasecmp(argv[1], "-sr16") ==0) shft=1;
    if (strcasecmp(argv[1], "-sr32") ==0) shft=2;
    if (shft>=0) {
//    if ((strcasecmp(argv[1], "-sr8")==0) { // read SDRAM through PIO
      if (argc<3) {printf("Need SDRAM address (hex) to read\r\n");return -1;}
           sa= strtol (argv[2],&cp,16);
      n=1; if (argc >3) n= strtol (argv[3],&cp,16);
      if ((devfd = open("/dev/fsdram", O_RDONLY))<0)  {printf("error opening /dev/fsdram\r\n"); return -1;}
//      printf("devfd=%d, sa=%x, n=%x\n",devfd, (int) sa,n);
      while (n>0) {
        i=n; if (i>(sizeof(usbuf)>>shft)) i=sizeof(usbuf)>>shft;
        if ((res=lseek(devfd,sa<<shft,0))<0) {
          printf("lseek failed, returned %d\n",res);
          close (devfd);
          return -1;
        }
        if ((res=read(devfd,usbuf,i<<shft))<(i<<shft)) {
          printf("read failed, returned %d, expected - %d\n",res, (i<<shft));
          close (devfd);
          return -1;
        }
// print buffer
        for (j=0;j<i;j++) {
//          if (res && ( ((sa+j) & 0x0f) == 0)) printf("\n%06x:",(int) (sa+j));
          if (res && ( ((sa+j) &  ((0x20 >> shft)-1)) == 0)) printf("\n%06x:",(int) (sa+j));
//          printf (" %4x", (int) usbuf[j]);
          if      (shft==0)  printf (" %2x", (int) usbuf8[j]);
          else if (shft==1)  printf (" %4x", (int) usbuf16[j]);
          else if (shft==2)  printf (" %8x", (int) usbuf32[j]);
          res=1;
        }
        sa += i;
        n  -= i;
      }
      printf("\n");
      close (devfd);
      return 0;
    }
    shft=-1;
    if (strcasecmp(argv[1], "-sw")   ==0) shft=1;
    if (strcasecmp(argv[1], "-sw8")  ==0) shft=0;
    if (strcasecmp(argv[1], "-sw16") ==0) shft=1;
    if (strcasecmp(argv[1], "-sw32") ==0) shft=2;
//    if (strcasecmp(argv[1], "-sw")==0) { // write SDRAM through PIO
    if (shft>=0)
        { // write SDRAM through PIO
      if (argc<3) {printf("Need SDRAM address (hex) to write data\r\n");return -1;}
      if (argc<4) {printf("Need SDRAM data (hex) to write to SDRAM\r\n");return -1;}
           sa= strtol (argv[2],&cp,16);
      uld=(unsigned long) strtoll (argv[3],&cp,16);
      n=1;   if (argc >4) n=   (unsigned long) strtoll (argv[4],&cp,16);
      uli=0; if (argc >5) uli= (unsigned long) strtoll (argv[5],&cp,16);
//  unsigned short usbuf[FPCF_SDBUFFER_SIZE];
//  unsigned char  * usbuf8 =  (unsigned char *)  usbuf;
//  unsigned short * usbuf16 = (unsigned short *) usbuf;
//  unsigned long  * usbuf32 = (unsigned long *)  usbuf;

      if ((devfd = open("/dev/fsdram", O_RDWR))<0)  {printf("error opening /dev/fsdram\r\n"); return -1;}
      while (n>0) {
        i=n; if (i>(sizeof(usbuf)>>shft)) i=sizeof(usbuf)>>shft;
//        for (j=0;j<i;j++) {usbuf[j]=uld; uld+=uli;}
        if      (shft==0) for (j=0;j<i;j++) {usbuf8[j] =uld; uld+=uli;}
        else if (shft==1) for (j=0;j<i;j++) {usbuf16[j]=uld; uld+=uli;}
        else if (shft==2) for (j=0;j<i;j++) {usbuf32[j]=uld; uld+=uli;}
        if ((res=lseek(devfd,sa<<shft,0))<0) {
          printf("lseek failed, returned %d\n",res);
          close (devfd);
          return -1;
        }
        if ((res=write(devfd,usbuf,i<<shft))<(i<<shft)) {
          printf("write failed, returned %d, expected - %d\n",res, (i<<shft));
          close (devfd);
          return -1;
        }
        sa += i;
        n  -= i;
      }

      close (devfd);
      return 0;
    }

    shft=-1;
    if (strcasecmp(argv[1], "-i2cr8")  ==0) shft=0;
    if (strcasecmp(argv[1], "-i2cr16") ==0) shft=1;
    if (shft>=0) { // read i2c bus0
      if (argc<3) {printf("Need I2C address (hex) to read: register address + 256* (slave address>>1)\r\n");return -1;}
      sa= strtol (argv[2],&cp,16);
      n=1; if (argc >3) n= strtol (argv[3],&cp,16);
      if (shft==1) {
         if ((devfd = open("/dev/xi2c16", O_RDONLY))<0)  {printf("error opening /dev/xi2c16\r\n"); return -1;}
      } else {
         if ((devfd = open("/dev/xi2c8",  O_RDONLY))<0)  {printf("error opening /dev/xi2c8\r\n"); return -1;}
      }
//      printf("devfd=%d, sa=%x, n=%x\n",devfd, (int) sa,n);
      while (n>0) {
        i=n; if (i>(sizeof(usbuf)>>shft)) i=sizeof(usbuf)>>shft;
        if ((res=lseek(devfd,sa<<shft,0))<0) {
          printf("lseek failed, returned %d\n",res);
          close (devfd);
          return -1;
        }
        if ((res=read(devfd,usbuf,i<<shft))<(i<<shft)) {
          printf("read failed, returned %d, expected - %d\n",res, (i<<shft));
          close (devfd);
          return -1;
        }
// print buffer
        for (j=0;j<i;j++) {
          if (res && ( ((sa+j) &  ((0x20 >> shft)-1)) == 0)) printf("\n%06x:",(int) (sa+j));
          if      (shft==0)  printf (" %2x", (int) usbuf8[j]);
//          else if (shft==1)  printf (" %4x", (int) usbuf16[j]);
          else if (shft==1)  printf (" %4x", ((((int) usbuf16[j])>>8) & 0xff) | ((((int) usbuf16[j]) << 8) & 0xff00)  );
//          else if (shft==2)  printf (" %8x", (int) usbuf32[j]);
          res=1;
        }
        sa += i;
        n  -= i;
      }
      printf("\n");
      close (devfd);
      return 0;
    }

    shft=-1;
    if (strcasecmp(argv[1], "-i2cw8")  ==0) shft=0;
    if (strcasecmp(argv[1], "-i2cw16") ==0) shft=1;
    if (shft>=0) { // write i2c bus0
      if (argc<3) {printf("Need I2C address (hex) to write: register address + 256* (slave address>>1)\r\n");return -1;}
      if (argc<4) {printf("Need data (hex) to write to i2c bus 0\r\n");return -1;}
           sa= strtol (argv[2],&cp,16);
      uld=strtol (argv[3],&cp,16);
      if (shft==1) {
         if ((devfd = open("/dev/xi2c16", O_RDWR))<0)  {printf("error opening /dev/xi2c16\r\n"); return -1;}
         uld= ((uld >>8) & 0xff) | ((uld <<8) & 0xff00);
      } else {
         if ((devfd = open("/dev/xi2c8",  O_RDWR))<0)  {printf("error opening /dev/xi2c8\r\n"); return -1;}
      }
      if ((res=lseek(devfd,sa<<shft,0))<0) {
        printf("lseek failed, returned %d\n",res);
        close (devfd);
        return -1;
      }
      if ((res=write(devfd,&uld,1<<shft))<(1<<shft)) {
        printf("write failed, returned %d, expected - %d\n",res, (1<<shft));
        close (devfd);
        return -1;
      }
      close (devfd);
      return 0;
    }
// end of i2c{r,w}{8,16}

         if (strcasecmp(argv[1], "-s")==0) { // read FPGA state
      if ((devfd = open("/dev/fpgaio", O_RDONLY))<0)  {printf("error opening /dev/fpgaio\r\n"); return -1;}
            d=ioctl(devfd, _IO(FPGACONF_GETSTATE,0), 0) ;
// add details...
        printf ("FPGA state is %x\r\n",(int) d);
        close (devfd);
      return 0;
    }

// now parse direct r/w commands and arguments
    iorw_args=0;
        if (strcasecmp(argv[1], "-r")==0)    iorw_args=FPGACONF_READREG;
        if (strcasecmp(argv[1], "-rl")==0)   iorw_args=FPGACONF_READREG_L;
        if (strcasecmp(argv[1], "-rh")==0)   iorw_args=FPGACONF_READREG_H;
        if (strcasecmp(argv[1], "-r4")==0)   iorw_args=FPGACONF_READREG4;
        if (strcasecmp(argv[1], "-rl4")==0)  iorw_args=FPGACONF_READREG_L4;
        if (strcasecmp(argv[1], "-rh4")==0)  iorw_args=FPGACONF_READREG_H4;
        if (strcasecmp(argv[1], "-w")==0)    iorw_args=FPGACONF_WRITEREG;
        if (strcasecmp(argv[1], "-w4")==0)   iorw_args=FPGACONF_WRITEREG4;
        if (strcasecmp(argv[1], "-rw")==0)   iorw_args=FPGACONF_RD_WAITSTATES;
        if (strcasecmp(argv[1], "-ww")==0)   iorw_args=FPGACONF_WR_WAITSTATES;
    if (iorw_args) {
// check args
       rd=0;
       ra=0;
       switch (iorw_args) {
       case FPGACONF_WRITEREG:
       case FPGACONF_WRITEREG4:
        {
             if (argc<4) {printf("Need 32-bit data (hex) to write to a register\r\n"); return -1;}
             rd= (unsigned long) strtoll (argv[3],&cp,16);
        }
      // fall to get ra
       case FPGACONF_READREG:
       case FPGACONF_READREG_L:
       case FPGACONF_READREG_H:
       case FPGACONF_READREG4:
       case FPGACONF_READREG_L4:
       case FPGACONF_READREG_H4:
        {
         if (argc<3) {printf("Need register address (hex) to read\r\n");return -1;}
             ra= (strtol (argv[2],&cp,16) & 0xff);
         break;         
        }
       case FPGACONF_WR_WAITSTATES:
         if (argc<3) {printf("Need value for rw_grp[i]_cfg (hex)\r\n");return -1;}
         if (argc<4) {
           ra=2;
           rd= (unsigned long) strtoll (argv[2],&cp,16);
         } else {
           ra= strtol (argv[2],&cp,16);
           rd= (unsigned long) strtoll (argv[3],&cp,16);
           if ((ra<1) || (ra>4)) { printf("address should be 1..4, you provided %ld\r\n",ra);return -1; }
         }
       case FPGACONF_RD_WAITSTATES:
         if (argc<3) {
           ra=2;
         } else {
           ra= strtol (argv[2],&cp,16);
           if ((ra<1) || (ra>4)) { printf("address should be 1..4, you provided %ld\r\n",ra);return -1; }
         }
       break;           
       default: {printf("unrecognised IORW command # %d\r\n",iorw_args);return -1;} 
      }
      if ((devfd = open("/dev/fpgaio", O_RDWR))<0)  {printf("error opening /dev/fpgaio\r\n"); return -1;}
      d=ioctl(devfd, _IO(iorw_args, ra ), rd); // works for both W and R
      printf ("%x\n",(int) d);
      close (devfd);
//      return d; 
      return 0; // OK
    }
    if (strcasecmp(argv[1], "-button")==0) {
       if ((devfd = open("/dev/fpgaconfi2c", O_RDWR))<0)  {printf("error opening /dev/fpgaconfi2c\r\n"); return -1;}
       d=(ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_PA_RD ),0)>>6) & 1;
       printf ("%d\n",(int) d);
       close (devfd);
       return d;
    } 
 
// read/write port A (JTAG to FPGA)
        if ((argv[1][1] == 'a') || (argv[1][1] == 'A')) { 
          if ((devfd = open("/dev/fpgaconfi2c", O_RDWR))<0)  {printf("error opening /dev/fpgaconfi2c\r\n"); return -1;}
          if (argc<3) { // read port A
            d=ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_PA_RD ),0);
            printf ("%x\n",(int) d);
          } else {     // write port A
            d=strtol (argv[2],&cp,16);    
            ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_PA_WR ),d);
          }
          close (devfd);
          return d;
        }
//FPGA programming - not needed anymore as it is possible just to "cat filename >/dev/fpgaconfjtag
//  #define FPGA_JTAG_ARG(tms, len, d) (((tms) << 11) | ((len) << 8) | ((d) & 0xff))
        if ((argv[1][1] == 't') || (argv[1][1] == 'T')) { // send/get JTAG command
          d=0; n= 0; i=0;
          if (argc>4) {
            d=(strtol (argv[4],&cp,16) & 0xff);
            n=(strtol (argv[3],&cp,16) & 0x7);
            i=(strtol (argv[2],&cp,16) & 0x1);
          } else if (argc>3) {
            d=(strtol (argv[3],&cp,16) & 0xff);
            n=(strtol (argv[2],&cp,16) & 0x7);
          } else if (argc>2) {
            d=(strtol (argv[2],&cp,16) & 0xff);
          }
          if ((devfd = open("/dev/fpgaconfi2c", O_RDWR))<0)  {printf("error opening /dev/fpgaconfi2c\r\n"); return -1;}
          j=ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_JTAG ),FPGA_JTAG_ARG(i, n, d ));
          printf ("JTAG returned %x\n", j);
          close (devfd);
          return 0;
        }
        if ((argv[1][1] == 'p') || (argv[1][1] == 'P')) { // program FPGA
//        if (argc<3) {
//            printf("Need FILENAME to load\r\n");
//            return -1;
//        }
          if ((devfd = open("/dev/fpgaconfi2c", O_RDWR))<0)  {printf("error opening /dev/fpgaconfi2c\r\n"); return -1;}
          if (argc>2) {
            if ((ifd=open(argv[2],O_RDONLY))<0) {printf("error opening bitstream file %s\r\n",argv[2]); close(devfd); return -1;}
          } else ifd=-1;  
          i=0;

          n=-1;
          if ( ifd>=0) {
            while ((i<1000) && (read(ifd,&charheadbuf[(i++) & 7],1)>0)) {
              j=0;
              while ((j<8) && (charheadbuf[(i+j) & 7]==syncseq[j])) j++;

              if (j==8) {n=i-8;break;}
/* 
            if (i<80) {
             bp=charheadbuf[i & 7];
             printf ("i= %d,j=%d,
charheadbuf[i & 7]=%d \n",i,j,bp);
            }
*/
            }
            if (n<0)  {printf("No <ff ff ff ff aa 99 55 66> syncseq found\r\n"); close(devfd); return -1;}
            printf ("Skipping header %d bytes long\n",n);
          }

//  while ((nr=read(ifd,dbi,USEBUFFERSIZE<<1))>0)
          // pulse PROGRAM pin;
          ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_PGM ),1);     // set PROGRAM on  (logic low)
          ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_PGM ),0);     // set PROGRAM off (logic high)
          retr=0;
          while ((retr < 100000) && ((ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_STAT ),0) & 1) == 0)) retr ++;
          printf ("waited for INIT high %d cycles\r\n",retr);
          if ((ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_STAT ),0) & 1) == 0) {
            close (ifd);
            close (devfd);
            printf("FPGA not ready\r\n");
            return -2;
          }
// actual programming
          ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_JTAG ),FPGA_JTAG_ARG(1, 5, 0   )); //step 1 - set Test-Logic-Reset state
          ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_JTAG ),FPGA_JTAG_ARG(0, 1, 0   )); //step 2 - set Run-Test-Idle state
          ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_JTAG ),FPGA_JTAG_ARG(1, 2, 0   )); //step 3 - set SELECT-IR state
          ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_JTAG ),FPGA_JTAG_ARG(0, 2, 0   )); //step 4 - set SHIFT-IR state
          ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_JTAG ),FPGA_JTAG_ARG(0, 5, 0xa0)); //step 5 - start of CFG_IN ***NOW 6 bits ***
          ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_JTAG ),FPGA_JTAG_ARG(1, 1, 0   )); //step 6 - finish CFG_IN
          ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_JTAG ),FPGA_JTAG_ARG(1, 2, 0   )); //step 7 - set SELECT-DR state
          ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_JTAG ),FPGA_JTAG_ARG(0, 2, 0   )); //step 8 - set SHIFT-DR state

// send 8-byte syncseq
          for (i=0; i<8; i++) {
                     j=ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_JTAG ),FPGA_JTAG_ARG(0, 0, syncseq[i] )); //shift 8 data bits
                printf("i=%d, j=%x, syncseq[i]=%x\n",i,j,(int) syncseq[i]);
          }

          testnum=7;
     retr=0;
          if (ifd>=0) {
            read(ifd,&b0,1);  b=b0;     //for (i=0;i<8;i++) {b=(b<<1) | (b0 & 1); b0>>=1;} b&=0xff;
            while (read(ifd,&b0,1)>0) {
testcs+=b;
testnum++;
             i= ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_JTAG ),FPGA_JTAG_ARG(0, 0, b ));  //shift 8 data bits
//          if (testnum<90) printf("num=%5x, wr= %2x, rd=%3x\n",testnum,(int) b, i );

              if (i & 0x100) { //readback mismatch, but printed are wrong data
                  printf("readback mismatch at %x - written:%x, read: %x\n",testnum,(int) b, i & 0xff);
              }

              b=b0;
//        for (i=0;i<8;i++) {b=(b<<1) | (b0 & 1); b0>>=1;} b&=0xff;

//       if ((retr & 0xfff)==0) {printf("\r\nretr=%d\r\n",retr);getchar ();}
//       if (retr <10) {printf("\r\nafter step9 (byte %d) - %d\r\n",retr,ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_STAT ),0));getchar ();}
       retr++;
            }
          } else {
            b0=0; b=b0;
            for (n=0;n<8;n++) {
             b0=0;
testcs+=b;
testnum++;
             i= ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_JTAG ),FPGA_JTAG_ARG(0, 0, b ));  //shift 8 data bits
             if (testnum<90) printf("num=%5x, wr= %2x, rd=%3x\n",testnum,(int) b, i );

              if (i & 0x100) { //readback mismatch, but printed are wrong data
                  printf("readback mismatch at %x - written:%x, read: %x\n",testnum,(int) b, i & 0xff);
              }

              b=b0;
//        for (i=0;i<8;i++) {b=(b<<1) | (b0 & 1); b0>>=1;} b&=0xff;

//       if ((retr & 0xfff)==0) {printf("\r\nretr=%d\r\n",retr);getchar ();}
//       if (retr <10) {printf("\r\nafter step9 (byte %d) - %d\r\n",retr,ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_STAT ),0));getchar ();}
       retr++;
            }
            close (devfd);
            return 0;
          } // end of test mopde  
testcs+=b;
testnum++;
          ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_JTAG ),FPGA_JTAG_ARG(0, 7, b   )); //shift 7 data bits
          ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_JTAG ),FPGA_JTAG_ARG(1, 1, (b<<7))); //step 10 - shift last data bit
          ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_JTAG ),FPGA_JTAG_ARG(1, 1, 0   )); //step 11 - set UPDATE-DR state
          ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_JTAG ),FPGA_JTAG_ARG(1, 2, 0   )); //step 12 - set SELECT-IR state
          ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_JTAG ),FPGA_JTAG_ARG(0, 2, 0   )); //step 13 - set SHIFT-IR state
          ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_JTAG ),FPGA_JTAG_ARG(0, 5, 0x30)); //step 14 - start of JSTART  ***NOW 6 bits ***
          ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_JTAG ),FPGA_JTAG_ARG(1, 1, 0   )); //step 15 - finish JSTART
          ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_JTAG ),FPGA_JTAG_ARG(1, 2, 0   )); //step 16 - set SELECT-DR state
          ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_JTAG ),FPGA_JTAG_ARG(0, 0, 0   )); //step 17 - set SHIFT-DR , clock startup
          ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_JTAG ),FPGA_JTAG_ARG(0, 0, 0   )); //step 17a - (total >=12 clocks)
          ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_JTAG ),FPGA_JTAG_ARG(1, 2, 0   )); //step 18 - set UPDATE-DR state
          ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_JTAG ),FPGA_JTAG_ARG(0, 1, 0   )); //step 19 - set Run-Test-Idle state
          printf ("FPGA status = %x\r\n", ioctl(devfd, _IO(FPGACONF_IOCTYPE, FPGA_STAT ),0));
      printf ("testcs = %x, testnum= %x (%d)\r\n", testcs,testnum,testnum);

          if ( ifd>=0) close (ifd);
          close (devfd);
          return 0;
        } 
        if (argv[1][1] == 'X') { // frequencies settings
          if (argc<3) {printf("Needs more args...\r\n"); return 0;}
          n= strtol (argv[2],&cp,10);
     if ((n<0) || (n>3)) {
        printf("Invalid clock number - %d\r\n", n);
        return -1;
     }
     if (argc<4) { // read clock (shadow)
       
       if ((devfd = open("/dev/fpgaclocks", O_RDONLY))<0)  {printf("error opening /dev/fpgaclocks\r\n"); return -1;}
//        f= ioctl(devfd, _IO(FPGA_CLOCK_IOCTYPE_RD, n ),0); // read current clock frequency
        i= ioctl(devfd, _IO(FPGA_CLOCK_IOCTYPE_RD, n ),0); // read current clock frequency
        close (devfd);
        if (i<0) {printf("Error reading clock %d, code=%d\r\n", n, -i); return -1;}
        f=i;
        f*=0.000001;
        if (i) printf("Clock %d is set to %eMHz\r\n",n,f);
        else   printf("Clock %d is OFF\r\n",n);
        return 0;
     }
          f= strtod (argv[3],&cp); // floating point now (1Hz resolution)

//====================
      if ((devfd = open("/dev/fpgaclocks", O_RDWR))<0)  {printf("error opening /dev/fpgaclocks\r\n"); return -1;}
      i=1000000*f; // integer in Hz
      switch (n) {
         case 0: {
           j= ioctl(devfd, _IO(FPGA_CLOCK_IOCTYPE, 0 ),i);
           break;
         }
         case 1: {
           j= ioctl(devfd, _IO(FPGA_CLOCK_IOCTYPE, 1 ),i);
           break;
         }
         case 2: {
           j= ioctl(devfd, _IO(FPGA_CLOCK_IOCTYPE, 2 ),i);
           break;
         }
         case 3: {
           j= ioctl(devfd, _IO(FPGA_CLOCK_IOCTYPE, 3 ),i);
           break;
         }
//         default:{
//           printf("Invalid clock number - %d\r\n", n);
//           return -1;
//         }
       }
       close (devfd);
       if (j<0) { // TODO: change later - too low, to high
           printf("Error setting clock, code=%d\r\n", -j);
           return -1;
       } else if (j==0) {
           printf("Clock %d turned off\r\n",n);
       } else {
           f=0.000001*j;
           printf("Set clock %d to %eMHz\r\n",n,f);
       }
      return 0;
    }


  if (argv[1][1] == 'x') { // frequencies settings
          if (argc<4) {printf("Needs more args...\r\n"); return 0;}
          n= strtol (argv[2],&cp,10);
//        i= strtol (argv[3],&cp,10);
          f= strtod (argv[3],&cp); // floating point now (1Hz resolution)
     i=1000000*f; // integer in Hz

//    if ((i<0) || (i>127)) {
//      printf ("frequency should be in the range of 0...127, not %d\n",i);

    if((f < CLOCK_LOW) || (f > CLOCK_HIGH)) {
      printf ("frequency should be in the range of %d...%d MHz, not %fMhz\n", CLOCK_LOW, CLOCK_HIGH, f);
      return -1;
    }

    if ((n<0) || (n>1)) {
      printf ("Only clocks 0 (fpga) and 1 (sensor) are supported, not %d\n",n);
      return -1;
    }
    devfd = open("/dev/circbuf", O_RDWR);  // this file will not init fpga and sensor
    if (devfd<0) { // check control OK
      printf ("Error opening %s\n","/dev/circbuf");
      return -1;
    }
    switch (n) {
      case 0: {j=ioctl(devfd, _CCCMD(CCAM_WPARS ,  P_CLK_FPGA  ), i);break;} // in Hz now!!
      case 1: {j=ioctl(devfd, _CCCMD(CCAM_WPARS ,  P_CLK_SENSOR), i);break;}
      default: j=-1;
    }
    if (j<0) printf ("Error setting clock %d to %dMHz\n",n,i);
    else  printf ("clock %d will be set to %dMHz when sensor will be programmed\n",n,i);
    close (devfd);
    return 0;
  }

//++++++++++++++++++++++++++++++++++++++++++++++++++++++

    
        if ((argv[1][1] == 'i') || (argv[1][1] == 'I')) { // i2c operations
          if ((argv[1][2] == 'r') || (argv[1][2] == 'R')) {
            if (argc<3) { // dumping all i2c registers from Cypress CLock chip
        sa=CY22393_SA;
//              bus=0;
                devfd = open("/dev/fpgaclocksi2c", O_RDONLY);

                printf ("open returned - %x\r\n",devfd);
        j= 0x58;
                printf("dumping all i2c data from slave address %x\r\n", (int) sa);
                for (i=0;i<j;i++) {
                  if ((i & 0x0f)==0) printf("\r\n%2x:",i);
                  d=ioctl(devfd, _IO(FPGA_CLOCK_IOCTYPE,FPGA_CLOCK_I2C_READREG), I2C_READARG ( 0,  sa, i));
                  printf(" %2lx", d);
                }
                printf ("\r\n");
                close(devfd);
                printf ("devfd closed\r\n");
                return 0;
            }
            if (argc<4) {printf("Needs more args...\r\n"); return 0;}

            sa= (strtol (argv[2],&cp,16) & 0xff);
            ra= (strtol (argv[3],&cp,16) & 0xff);
            devfd = open("/dev/fpgaclocksi2c", O_RDONLY);
            printf ("open returned - %x\r\n",devfd);

            d=ioctl(devfd, _IO(FPGA_CLOCK_IOCTYPE,FPGA_CLOCK_I2C_READREG), I2C_READARG (0, sa, ra)) ;
            printf ("i2c register = %lx\r\n", d);
            close(devfd);
          printf ("devfd closed\r\n");

            return 0;
          } else if  ((argv[1][2] == 'w') || (argv[1][2] == 'W')) {
  
            if (argc<5) {printf("Needs more args...\r\n"); return 0;}
            sa= (strtol (argv[2],&cp,16) & 0xff);
            ra= (strtol (argv[3],&cp,16) & 0xff);
            rd= (strtol (argv[4],&cp,16) & 0xff);
            devfd = open("/dev/fpgaclocksi2c", O_WRONLY);
            printf ("open returned - %x\r\n",devfd);

            d=ioctl(devfd, _IO(FPGA_CLOCK_IOCTYPE, FPGA_CLOCK_I2C_WRITEREG ),I2C_WRITEARG(0, sa, ra, rd));
            printf ("i2c returned - %lx\r\n",d);//168
            close(devfd);  printf ("devfd closed\r\n");
            return 0;
          } // if  ((argv[1][2] == 'w') ...
   }

   if  ((argv[1][1] == 'c') || (argv[1][1] == 'C')){

//        if (argc<3) {printf("Needs more args (bit #, [op])\r\n"); return -1;}
        if ((devfd = open("/dev/fpgaio", O_RDWR))<0)  {printf("error opening /dev/fpgaio\r\n"); return -1;}
          if (argc<3) { // print status register
          res= ioctl(devfd, _IO(FPGACONF_CONTROL_REG,FPGACONF_CR_SHADOW), 0);
          i=   ioctl(devfd, _IO(FPGACONF_CONTROL_REG,FPGACONF_CR_SHADOW1), 0); // MSB ioctl returns positive or error
          res |= ((i << 1) & 0x80000000);
          printf ("%x\n",res);
          close (devfd);
          return 0;
        }
       a=(strtol (argv[2],&cp,16) & 0x1f);
       res=0;
       if (argc>3) {
         res=(strtol (argv[3],&cp,16) & 0x3);
         i=ioctl(devfd, _IO(FPGACONF_CONTROL_REG, FPGACONF_CR_MODIFY), res | (a<<2));
         j=ioctl(devfd, _IO(FPGACONF_CONTROL_REG, FPGACONF_CR_MODIFY), 0   | (a<<2));
         printf ("CR[%x]=%x (was %x)\r\n",a,j,i);
       } else printf("%x\n", ioctl(devfd, _IO(FPGACONF_CONTROL_REG, FPGACONF_CR_MODIFY), 0   | (a<<2))); // quiet mode, for scripts analysing output
       close(devfd);
       return 0;
   }

   if (strcasecmp(argv[1], "-sysmem")==0) { // test system memory - now - just fro intereference, not a real memory test
     if (argc<3) {printf("Number of 128KB chunks (decimal)to test is required\r\n");return -1;}
     ll=0x20000;
     n= strtol (argv[2],&cp,10);
     if (argc >3) {
        seed = strtol (argv[3],&cp,16);
        if (argc >4) {
          ll= strtol (argv[4],&cp,16);
        }
     } else seed=0;
     if (n>4096) n=4096;
     ll=ll>>2; // 32-bit

     for (i=0; i<n; i++) {
       memchunks[i] = (int *) malloc(ll<<2);
       if (!memchunks[i]) {
        n=i+1;
        break;
       }
     }
     printf ("testing %d (0x%x) memory chunks of %d (0x%x) bytes each... ",n,n, (int) (ll<<2),(int) (ll<<2));
     fflush(NULL);
     res=seed;
     for (i=0; i<n; i++) for (j=0; j<ll; j++) {
       memchunks[i][j]= (res <<16) || res;
       res++;
     }
//     i=n/2; j=ll/2;  memchunks[i][j]=0x12345678; // test error
     res=seed;
     mn=0;
     for (i=0; i<n; i++) for (j=0; j<ll; j++) {
       if (memchunks[i][j]!= ((res <<16) || res)) {
         if (mn<1000) printf ("\n chunk 0x%x, word 0x%x expected 0x%x read 0x%x",i,j,((res <<16) || res),memchunks[i][j]);
         fflush(NULL);
         mn++;
       }
       res++;
     }
     for (i=0; i<n; i++)  free(memchunks[i]);
     if (mn==0) printf ("done\n");
     else printf ("\nNumber of errors - %d (0x%x)\n",mn,mn);
     return 0;
   }
   printf(short_usage);
   return 0;    
}

---